Programmable logic device with cascading DSP slices

An integrated circuit comprising:

• a plurality of digital signal processing (DSP) elements, including a first DSP element and a second DSP element, each of the first DSP element and the second DSP element having substantially identical structure and each of the first DSP element and the second DSP element comprising a respective switch connected to a respective hardwired adder;
• a first signal line and a second signal line connecting the first DSP element to the second DSP element;
• the first signal line connecting a first output cascade port of the first DSP element to a first input cascade port of the second DSP element;
• the second signal line connecting a second output cascade port of the first DSP element to a second input cascade port of the second DSP element;
• the first output cascade port being on an input side of a multiplier of the first DSP element;
• the first input cascade port being on an input side of a multiplier of the second DSP element;
• the second output cascade port being on an output side of both the hardwired adder of the first DSP element and the multiplier of the first DSP element;
• and
• the second input cascade port being on an input side of the hardwired adder of the second DSP element and on an output side of the multiplier of the second DSP element;
• wherein the first DSP element is connected to the second DSP element for cascading thereof on pre- and post-multiplier sides of the second DSP element without having to pass through programmable interconnects of a programmable logic device.

An integrated circuit comprising:

• configurable logic blocks;
• programmable interconnect circuitry connecting to some of the configurable logic blocks;
• the configurable logic blocks configurable for issuing signals to a digital signal processing (DSP) slice and connectable to the DSP slice via the programmable interconnect circuitry;
• the DSP slice comprising:
• a feedback port;
• a DSP-slice output port;
• and
• a direct connection between the DSP-slice output port and the feedback port;
• a first signal line and a second signal line for connecting the DSP slice to an upstream DSP slice;
• the first signal line connecting the DSP-slice output port of the DSP slice to a DSP-slice input port of the upstream DSP slice;
• the second signal line connecting an output cascade port of the DSP slice to an input cascade port of the upstream DSP slice;
• the output cascade port being on an input side of a multiplier of the DSP slice;
• the input cascade port being on an input side of a multiplier of the upstream DSP slice;
• the DSP-slice output port being on an output side of both a hardwired adder of the DSP slice and the multiplier of the DSP slice;
• and
• the DSP-slice input port being on an input side of a hardwired adder of the upstream DSP slice and on an output side of the multiplier of the upstream DSP slice;
• wherein the DSP slice is connected to the upstream DSP slice for cascading thereof on pre- and post-multiplier sides of the upstream DSP slice without having to pass through programmable interconnects of the programmable interconnect circuitry.

A circuit comprising:

• a plurality of DSP slices, including an upstream DSP slice and a downstream DSP slice, each of the upstream and downstream DSP slices including:
• a cascade input port;
• a DSP-slice input port;
• a DSP-slice output port;
• a cascade output port;
• first and second operand input ports;
• a product generator having a multiplier port connected to the first operand input port, a multiplicand port connected to the second operand input port, and a product port;
• and
• an adder having a first addend port connected to the product port, a second addend port connected to the cascade input port, and a sum port;
• a first signal line and a second signal line for connecting the downstream DSP slice to the upstream DSP slice;
• the first signal line connecting the DSP-slice output port of the downstream DSP slice to the DSP-slice input port of the upstream DSP slice;
• the second signal line connecting the cascade output port of the downstream DSP slice to the cascade input port of the upstream DSP slice;
• the cascade output port of the downstream DSP slice being on an input side of the product generator of the downstream DSP slice;
• the cascade input port of the upstream DSP slice being on an input side of the product generator of the upstream DSP slice;
• the DSP-slice output port of the downstream DSP slice being on an output side of both the adder of the downstream DSP slice and the product generator of the downstream DSP slice;
• and
• the DSP-slice input port of the upstream DSP slice being on an input side of the adder of the upstream DSP slice and on an output side of the product generator of the upstream DSP slice;
• wherein the downstream DSP slice is connected to the upstream DSP slice for cascading thereof on pre- and post-product generator sides of the upstream DSP slice without having to pass through programmable interconnects of programmable interconnect circuitry.

A system comprising:

• configurable logic blocks;
• interconnect lines;
• a plurality of switch matrices programmably connected to the interconnect lines;
• a column of DSP slices, each DSP slice including first and second operand input ports programmably connected to the interconnect lines via at least one of the switch matrices;
• a configuration memory storing configuration data defining a configuration of the logic blocks, switch matrices, and DSP slices of the column of DSP slices;
• a first signal line and a second signal line for connecting a downstream DSP slice to an adjacent upstream DSP slice in the column of DSP slices;
• the first signal line connecting a DSP-slice output port of the downstream DSP slice to a DSP-slice input port of the upstream DSP slice;
• the second signal line connecting a cascade output port of the downstream DSP slice to a cascade input port of the upstream DSP slice;
• the cascade output port being on an input side of a product generator of the downstream DSP slice;
• the cascade input port being on an input side of a product generator of the upstream DSP slice;
• the DSP-slice output port being on an output side of both an adder of the downstream DSP slice and the product generator of the downstream DSP slice;
• and
• the DSP-slice input port being on an input side of an adder of the upstream DSP slice and on an output side of a product generator of the upstream DSP slice;
• wherein the downstream DSP slice is connected to the upstream DSP slice for cascading thereof on pre- and post-product generator sides of the upstream DSP slice without having to pass through the plurality of switch matrices programmably connected to the interconnect lines.

A DSP element in an integrated circuit comprising:

• a first switch;
• a multiplier circuit connected to the first switch;
• a second switch, the second switch connected to the multiplier circuit;
• an adder circuit connected to the second switch;
• wherein the integrated circuit comprises another DSP element having substantially identical structure to the DSP element and is coupled to the DSP element via dedicated signal lines including:
• a first signal line and a second signal line for connecting the DSP element to the other DSP element;
• the first signal line connecting a DSP-element output port of the DSP element to a DSP-element input port of the other DSP element;
• the second signal line connecting a cascade output port of the DSP element to a cascade input port of the other DSP element;
• the cascade output port being on an input side of the multiplier circuit of the DSP element;
• the cascade input port being on an input side of the multiplier circuit of the other DSP element;
• the DSP-element output port being on an output side of both the adder circuit of the DSP element and the multiplier circuit of the DSP element;
• and
• the DSP-element input port being on an input side of the adder circuit of the other DSP element and on an output side of the multiplier circuit of the other DSP element;
• wherein the DSP element is connected to the other DSP element for cascading thereof on pre- and post-multiplier circuit sides of the other DSP element without having to pass through programmable interconnects of programmable interconnect circuitry of the integrated circuit.