# US 7,471,559 B2 · Semiconductor memory device for storing multilevel data

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- Number: US 7,471,559 B2
- Document ID: US7471559B2
- Status: Granted
- Kind: B2
- Application number: 11/693,213
- Filed: 2007-03-29
- Published: 2007-10-18
- Granted: 2008-12-30
- Earliest claimed: 2006-04-13
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Noboru Shibata
- Web page: https://patentgrep.com/patent/US7471559B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/12: Programming voltage switching circuits
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- G11C 2211/5649: Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
- G11C 2211/565: Multilevel memory comprising elements in triple well structure
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels; and
a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array, writes a threshold level lower than an original threshold level, and which, when not writing a second memory cell adjacent to the first memory cell consecutively, writes the original threshold level into the first memory cell.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first memory cell, after writing the original threshold level into the first memory cell, does not write the second memory cell in the next writing and writes a third memory cell away from the first memory cell on the second memory cell side.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the second memory cell is kept at a threshold level in erasure.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, when reading one of an n number of threshold levels, 1, 2, . . . , n, stored in the memory cell, precharges a specific voltage in the drain of the memory cell and changes the gate voltage of the memory cell to read threshold levels k, k+h, . . . , J−h, J (k, h, i, and n are natural numbers, where 0≦k≦n, 0≦J≦n, k<J, h<n).

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, wherein the control circuit, when the threshold level of the memory cell has reached i in the write sequence, omits the verify operations at threshold level i−m (i<n, m is an integer) and below.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, when verifying a write sequence in which one of an n number of threshold levels, 1, 2, . . . , n, is stored into the memory cell, precharges a specific voltage in the drain of the memory cell and changes the gate voltage of the memory cell to read threshold levels k, k+h, . . . , J−h, J (k, h, i, and n are natural numbers, where 0≦k≦n, 0≦J≦n, k<J, h<n).

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein the control circuit, when the threshold level of the memory cell has reached i in the write sequence, omits the verify operations at threshold level i−m (i<n, m is an integer) and below.

### Claim 8 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, when verifying a write sequence in which one of an n number of threshold levels is stored into the memory cell, precharges a specific voltage in the drain of the memory cell and changes the gate voltage of the memory cell to read threshold levels 1, . . . , k (k+h≦n, k and h are natural numbers) and, when level i has been reached, omits the verify operations at level i−1 and below.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, when verifying a write sequence in which one of an n number of threshold levels, 1, 2, . . . , n, stored in the memory cell is read, precharges a specific voltage in the drain of the memory cell, supplies a verify voltage lower than an original verify voltage to the gate of the memory cell to read threshold levels from the memory cell sequentially, and then precharges a specific voltage in the drain of the memory cell, and supplies the original verify voltage to the gate of the memory cell to read threshold levels from the memory cell sequentially.

### Claim 10 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, in a write verify operation of storing one of an n number of threshold levels into the memory cell, precharges a specific voltage in the drain of the memory cell, changes the gate voltage of the memory cell to read even-numbered threshold levels consecutively and then precharges a specific voltage in the drain of the memory cell to read odd-numbered threshold levels consecutively.

### Claim 11 (depends on 1)

The semiconductor memory device according to claim 1, wherein the control circuit, when verifying a write sequence in which one of an n number of threshold levels, 1, 2, . . . , n, stored in the memory cell is read, precharges a specific voltage in the drain of the memory cell, supplies a verify voltage lower than an original verify voltage to the gate of the memory cell to read even-numbered threshold levels from the memory cell, and then precharges a specific voltage in the drain of the memory cell, supplies the original verify voltage to the gate of the memory cell to read even-numbered threshold levels consecutively from the memory cell, and then precharges a specific voltage in the drain of the memory cell, supplies a verify voltage lower than the original verify voltage to the gate of the memory cell to read odd-numbered threshold levels from the memory cell consecutively, and then precharges a specific voltage in the drain of the memory cell, supplies the original verify voltage to the gate of the memory cell to read odd-numbered threshold levels from the memory cell consecutively.

### Claim 12 (depends on 1)

The semiconductor memory device according to claim 1, wherein the second memory cell is adjacent to the first memory cell in the direction of either the word line or the bit line.

### Claim 13 (depends on 1)

The semiconductor memory device according to claim 1, wherein the second memory cell is adjacent to the first memory cell in one of the direction of the word line and the direction of the bit line.

### Claim 14

A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels; and
a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array and further writing a second memory cell adjacent to the first memory cell consecutively, writes a threshold level lower than an original threshold level and which, when not writing the second memory cell adjacent to the first memory cell consecutively, writes the first memory cell at a decreased write speed.

### Claim 15 (depends on 14)

The semiconductor memory device according to claim 14, wherein the control circuit decreases the write speed when receiving a specific command.

### Claim 16

A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels; and
a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array, writes a threshold level lower than an original threshold level and which, when not writing a second memory cell adjacent to the first memory cell consecutively, keeps the first memory cell at the lower threshold level and, when writing one of said plurality of threshold levels into the second memory cell, reads the threshold level from the first memory cell and, after writing a specific threshold level into the second memory cell, writes the original threshold level into the first memory cell on the basis of the result of the reading.

### Claim 17 (depends on 16)

The semiconductor memory device according to claim 16, wherein the control circuit, when writing the second memory cell adjacent to the first memory cell consecutively, writes a threshold level lower than the original level into the second memory cell and then writes the original threshold level into the first memory cell.

### Claim 18 (depends on 16)

The semiconductor memory device according to claim 16, further comprising a data storage circuit which stores the data read from the first memory cell.