# US 7,467,316 B2 · System for clock synchronization for modules in an analytical device

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- Number: US 7,467,316 B2
- Document ID: US7467316B2
- Status: Granted
- Kind: B2
- Application number: 11/311,544
- Filed: 2005-12-19
- Published: 2007-06-21
- Granted: 2008-12-16
- Earliest claimed: 2005-12-19
- Assignees: Agilent Technologies, Inc.
- Inventors: Robert P. Rhodes
- Web page: https://patentgrep.com/patent/US7467316B2

## CPC

- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system for synchronizing clock signals in an analytical device includes a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal, and a second module including a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal. The second module includes a clock generator configured to receive the timing reference signal and the local clock signal and is configured to adjust a timing output of the second module so that the timing of the second module is synchronized to the master clock signal.

## Claims

### Claim 1

A system for synchronizing clock signals in an analytical device, comprising:
a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal;
a second module including a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal, wherein the second module includes a clock generator configured to receive the timing reference signal and the local clock signal and is configured to adjust a timing output of the second module so that the timing of the second module is synchronized to the master clock signal;
a counter configured to determine a number of pulses of the local clock signal that occur between a first pulse and second pulse of the timing reference signal;
an adder configured to determine a difference between the number of pulses of the local clock signal that occur between the first pulse and second pulse of the timing reference signal and a minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
a register configured to add the excess local clock cycles to the ancillary (ADC) clock signal and provide a first result; and
a comparator configured to compare the output of the register with a threshold value, wherein when the output of the register exceeds the threshold value, the comparator causes the ancillary (ADC) clock signal to be extended and causes the threshold value to be subtracted from the register, wherein any remainder in the register is applied to a subsequent ancillary (ADC) clock signal cycle.

### Claim 2 (depends on 1)

The system of claim 1, wherein the subsequent ancillary (ADC) clock signal is synchronized to the master clock signal.

### Claim 3 (depends on 2)

The system of claim 2, wherein the excess local clock cycles are apportioned between pulses of the timing reference signal.

### Claim 4 (depends on 3)

The system of claim 3, wherein one of a plurality of ancillary (ADC) clock signals is extended when the output of the register exceeds the threshold value.

### Claim 5 (depends on 1)

The system of claim 1, wherein the analytical device comprises a gas chromatograph and the ancillary (ADC) clock signal is part of a detector.

### Claim 6 (depends on 1)

The system of claim 1, in which a timing edge of the command signal aligns with a pulse associated with the master clock signal, and in which a pulse associated with the timing reference signal occurs on an edge of the local clock signal following the timing edge signal.

### Claim 7

A system for synchronizing clocks in an analytical device, comprising:
a timing command generator configured to generate a command signal, the command signal related to a master clock signal;
a command interpreter configured to generate a timing reference signal related to the command signal and a local clock signal;
a counter configured to determine a number of pulses of the local clock signal that occur between a first and second pulse of the timing reference signal;
an adder configured to determine a difference between the number of pulses of the local clock signal that occur between a first pulse and a second pulse of the timing reference signal and a minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
a register configured to add the excess local clock cycles to the ancillary (ADC) clock signal and provide a first result; and
a comparator configured to compare the output of the register with a threshold value, wherein when the output of the register exceeds the threshold value, the comparator causes the ancillary (ADC) clock signal to be extended and causes the threshold value to be subtracted from the register, wherein any remainder in the register is applied to a subsequent ancillary (ADC) clock signal cycle.

### Claim 8 (depends on 7)

The system of claim 7, wherein the subsequent ancillary (ADC) clock signal is synchronized to the master clock signal.

### Claim 9 (depends on 8)

The system of claim 8, wherein the excess local clock cycles are apportioned between pulses of the timing reference signal.

### Claim 10 (depends on 9)

The system of claim 9, wherein one of a plurality of ancillary (ADC) clock signals is extended when the output of the register exceeds the threshold value.

### Claim 11 (depends on 7)

The system of claim 7, wherein the analytical device comprises a gas chromatograph and the ancillary (ADC) clock signal is part of a detector.

### Claim 12 (depends on 7)

The system of claim 7, in which a timing edge of the command signal aligns with a pulse associated with the master clock signal, and in which a pulse associated with the timing reference signal occurs on an edge of the local clock signal following the timing edge signal.

### Claim 13

A method for synchronizing clocks in an analytical device, comprising:
generating a command signal, the command signal related to a master clock signal;
generating a timing reference signal related to the command signal and a local clock signal;
determining a number of pulses of the local clock signal that occur between a first pulse and a second pulse of the timing reference signal;
determining a minimum number of local clock cycles to generate an ancillary (ADC) clock signal;
determining a difference between the number of pulses of the local clock signal that occur between the first pulse and the second pulse of the timing reference signal and the minimum number of local clock cycles to generate an ancillary (ADC) clock signal, the difference representing a number of excess local clock cycles;
adding the excess local clock cycles to the ancillary (ADC) clock signal to provide a first result; and
comparing the first result with a threshold value, wherein when the first result exceeds the threshold value, modifying the ancillary (ADC) clock signal and subtracting the threshold value from the first result; and
applying any remainder after the subtraction to a subsequent ancillary (ADC) clock signal cycle.

### Claim 14 (depends on 13)

The method of claim 13, wherein the modified ancillary (ADC) clock signal is synchronized to the master clock signal.

### Claim 15 (depends on 14)

The method of claim 14, wherein the excess local clock cycles are apportioned between pulses of the timing reference signal.

### Claim 16 (depends on 15)

The method of claim 15, wherein one of a plurality of ancillary (ADC) clock signals is extended when the first result exceeds the threshold value.

### Claim 17 (depends on 13)

The method of claim 13, wherein the analytical devices comprises a gas chromatograph and the ancillary (ADC) clock signal is a detector.

### Claim 18 (depends on 13)

The method of claim 13, in which a timing edge of the command signal aligns with a pulse associated with the master clock signal, and in which a pulse associated with the timing reference signal occurs on an edge of the local clock signal following the timing edge signal.