# US 7,467,242 B2 · Method and system for dynamic FIFO flow control

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- Number: US 7,467,242 B2
- Document ID: US7467242B2
- Status: Granted
- Kind: B2
- Application number: 10/436,790
- Filed: 2003-05-13
- Published: 2004-12-02
- Granted: 2008-12-16
- Earliest claimed: 2003-05-13
- Assignees: VIA Technologies, Inc.
- Inventors: Hsilin Huang
- Web page: https://patentgrep.com/patent/US7467242B2

## CPC

- G06F 5/10: having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory {(G06F5/065 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

## Claims

### Claim 1

A method of optimally performing read operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
a) detecting an asserted read enable signal at the first FIFO device, wherein a first read pointer holds an address to the data entry to be read in a first FIFO memory in the first FIFO device;
b) detecting one or more obsolete data entries starting at the address held by the first read pointer;
c) loading the address of the next valid data entry into the first read pointer;
d) receiving a valid entry at the control circuit; and
e) determining whether the received valid entry is a header entry.

### Claim 2 (depends on 1)

The method of claim 1, further comprising the step of detecting an asserted write enable signal at the first FIFO device, wherein a first write pointer holds an address to be written to in the first FIFO memory.

### Claim 3 (depends on 1)

The method of claim 1, wherein the valid entry comprises graphics related data.

### Claim 4 (depends on 3)

The method of claim 3, wherein the valid entry comprises data associated with a triangle.

### Claim 5 (depends on 1)

The method of claim 1, wherein the received valid entry is a header entry.

### Claim 6 (depends on 5)

The method of claim 5, wherein the header entry comprises an identification tag for identifying the triangle.

### Claim 7 (depends on 6)

The method of claim 6, further comprising the step of writing the received header entry into a second FIFO device, setting a bit stored in a flip flop to logical zero wherein the flip flop corresponds to the triangle, sending the header data of the received header entry to an arithmetic logic unit (ALU) wherein the ALU is included in the control circuit, and sending the identification tag to a controller coupled to the ALU.

### Claim 8 (depends on 7)

The method of claim 7, further comprising the step of processing the header data sent to the ALU.

### Claim 9 (depends on 8)

The method of claim 8, further comprising the step of setting a bit in a register coupled to the ALU to logical one, wherein the bit corresponds to the triangle.

### Claim 10 (depends on 9)

The method of claim 9, further comprising the step of determining whether the triangle is rejected or culled.

### Claim 11 (depends on 10)

The method of claim 10, wherein the triangle associated with the header entry is not rejected or culled.

### Claim 12 (depends on 11)

The method of claim 11, further comprising the step of setting the bit stored in the flip flop associated with the triangle to logical zero.

### Claim 13 (depends on 10)

The method of claim 10, wherein the triangle is rejected or culled.

### Claim 14 (depends on 13)

The method of claim 13, further comprising the step of setting the bit stored in the flip flop associated with the triangle to logical one.

### Claim 15 (depends on 1)

The method of claim 1, wherein the received valid entry is not a header entry.

### Claim 16 (depends on 15)

The method of claim 15, wherein the valid entry comprises a first identification tag for identifying the triangle with which the received valid entry is associated.

### Claim 17 (depends on 16)

The method of claim 16, wherein the valid entry comprises a second identification tag for differentiating the last valid entry associated with the triangle.

### Claim 18 (depends on 17)

The method of claim 17, further comprising the step of determining whether the triangle is rejected or culled.

### Claim 19 (depends on 18)

The method of claim 18, wherein the triangle is not rejected or culled.

### Claim 20 (depends on 19)

The method of claim 19, further comprising the step of determining whether a new triangle is being written to the first FIFO device.

### Claim 21 (depends on 20)

The method of claim 20, wherein the determining step further comprises the step of comparing the first identification tag of the current valid entry to a third identification tag of the previous valid entry wherein the third identification identifies the triangle with which the previously received valid entry is associated.

### Claim 22 (depends on 21)

The method of claim 21, wherein the new triangle is not being written to the first FIFO device.

### Claim 23 (depends on 22)

The method of claim 22, further comprising the step of writing the valid entry to the first FIFO memory at the address held by the first write pointer.

### Claim 24 (depends on 21)

The method of claim 21, wherein the new triangle is being written to the first FIFO device.

### Claim 25 (depends on 24)

The method of claim 24, further comprising the step of writing the valid entry to the first FIFO memory at the address held by the first write pointer, and updating a second FIFO device wherein the second FIFO device is coupled to the first FIFO device.

### Claim 26 (depends on 25)

The method of claim 25, wherein the updating step further comprising writing the address held by the first write pointer into the second FIFO device and incrementing a second write pointer by one wherein the second write pointer holds an address to be written to a second FIFO memory of the second FIFO device.

### Claim 27 (depends on 18)

The method of claim 18, wherein the triangle is rejected or culled.

### Claim 28 (depends on 27)

The method of claim 27, wherein the valid entry is not written into the first FIFO device.

### Claim 29

A method of optimally performing read operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
detecting an asserted read enable signal at the first FIFO device, wherein a first read pointer holds an address to the data entry to be read in a first FIFO memory in the first FIFO device;
checking a first identification tag of the data entry;
detecting one or more obsolete data entries starting at the address held by the first read pointer;
loading the address of the next valid data entry into the first read pointer; and
detecting an asserted write enable signal at the first FIFO device, wherein a first write pointer holds an address to be written to in the first FIFO memory.

### Claim 30 (depends on 29)

The method of claim 29, wherein the valid entry to be read is graphics related data.

### Claim 31 (depends on 30)

The method of claim 30, wherein the valid entry comprises data associated with a triangle.

### Claim 32 (depends on 31)

The method of claim 31, wherein the first identification tag of the valid entry identifies the triangle.

### Claim 33 (depends on 32)

The method of claim 32, further comprising the step of checking a bit corresponding to the triangle in a register to verify whether a header entry of the triangle has been processed.

### Claim 34 (depends on 33)

The method of claim 33, wherein the header entry of the triangle has been processed.

### Claim 35 (depends on 34)

The method of claim 34, further comprising the step of determining whether the triangle is rejected or culled.

### Claim 36 (depends on 35)

The method of claim 35, wherein the triangle is not rejected or culled.

### Claim 37 (depends on 36)

The method of claim 36, further comprising the step of determining if the data entry to be read is the last entry of the triangle.

### Claim 38 (depends on 37)

The method of claim 37, wherein the determining step further comprising the step of checking a second identification tag of the data entry, wherein the second identification tag differentiates the last data entry of the triangle.

### Claim 39 (depends on 38)

The method of claim 38, wherein the data entry to be read is the last entry of the triangle.

### Claim 40 (depends on 39)

The method of claim 39, further comprising the step of reading the data entry from the first FIFO memory at the address held by the first read pointer.

### Claim 41 (depends on 40)

The method of claim 40, further comprising the step of incrementing by one the address held by the first read pointer, and incrementing the address held by a second read pointer by one wherein the second read pointer holds an address in a second FIFO device coupled to the first FIFO device.

### Claim 42 (depends on 38)

The method of claim 38, wherein the data entry to be read is not the last entry of the triangle.

### Claim 43 (depends on 42)

The method of claim 42, further comprising the step of reading the data entry from the first FIFO memory at the address held by the first read pointer, wherein the data of the data entry is read into an algorithmic logic unit (ALU) included in the control circuit and identification tags of the data entry are read into a controller coupled to the ALU.

### Claim 44 (depends on 43)

The method of claim 43, further comprising the step of incrementing by one the address held by the first read pointer.

### Claim 45 (depends on 35)

The method of claim 35, wherein the triangle is rejected or culled.

### Claim 46 (depends on 45)

The method of claim 45, further comprising the step of setting a first signal to logical one, wherein the first signal signifies to the first FIFO device that the next one or more data entries are obsolete.

### Claim 47 (depends on 46)

The method of claim 46, further comprising the step of performing a read operation in a second FIFO device coupled to the first FIFO device wherein the output of the read operation is loaded into the first read pointer of the first FIFO device, and incrementing the address held by a second read pointer by one wherein the second read pointer holds an address in the second FIFO device.

### Claim 48 (depends on 33)

The method of claim 33, wherein the header entry of the triangle has not been processed.

### Claim 49 (depends on 33, 48)

The method of claim 48, further comprising the step of repeating the checking step of claim 33.

### Claim 50

A method of optimally performing write operations in a first FIFO device with a control circuit coupled to the first FIFO device, the method comprising:
a) detecting an asserted write enable signal at the first FIFO device, wherein a first write pointer holds an address to be written to in the first FIFO memory;
b) detecting one or more obsolete data entries starting at the address held by the first write pointer;
c) loading the address of the next valid data entry into the first write pointer;
d) receiving a valid entry at the control circuit; and
e) determining whether the received valid entry is a header entry.