Processing unit having decimal floating-point divider using Newton-Raphson iteration
AssigneeWisconsin Alumni Research Foundation
InventorsLiang-Kai Wang, Michael J. Schulte
Life of this patent
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Abstract
A decimal floating-point divider is described that implements efficient hardware-based techniques for performing decimal floating-point division. The divider uses an accurate piecewise linear approximation to obtain an initial estimate of a divisor's reciprocal. The divider improves the initial estimate of the divisor's reciprocal using a modified form of Newton-Raphson iteration. The divider multiplies the estimated divisor's reciprocal by the dividend to produce a preliminary quotient. The preliminary quotient is rounded to produce the final decimal floating-point quotient.
Claims20
A processing circuit comprising a decimal floating-point divider circuit that includes a lookup, circuit that stores decimal data in a densely packet decimal (DPD) format for use in computing an initial approximation of a decimal divisor's reciprocal, a nine's compliment circuit and a multiplier circuit to perform Newton-Raphson iterations to output a decimal floating-point quotient.
A processing circuit comprising a decimal floating-point divider circuit that includes input circuits to receive a decimal dividend and a decimal divisor, a nine's compliment circuit and a multiplier circuit to perform Newton-Raphson iterations to output a decimal floating-point quotient,
- wherein the decimal multiplier circuit computes an initial approximation of the divisor's reciprocal according to the following equation:
- R
- 0
- =
- X
- m
- +
- X
- L
- _
- +
- 10
- -
- n
- (
- X
- M
- +
- 5
- ×
- 10
- -
- k
- -
- 1
- )
- 2
- ,
- where XM represents a k-digit more significant part of an n-digit divisor, X, and XL represents an (n−k)-digit less significant part of X.
A decimal floating-point divider circuit comprising:
- input circuits to receive a decimal floating-point dividend and a decimal floating-point divisor;
- a lookup circuit that stores decimal data in a densely packet decimal (DPD) format for use in computing an initial approximation of the divisor's reciprocal,
- a nine's complement circuit;
- a decimal multiplier circuit;
- wherein the lookup circuit, the nine's complement circuit and the decimal multiplier circuit compute initial approximation of the divisor's reciprocal,
- wherein the decimal multiplier circuit further (a) performs Newton-Raphson iterations to compute an improved approximation of the divisor's reciprocal based on the initial approximation, and (b) multiplies the dividend by the improved approximation to produce a preliminary decimal quotient;
- an incrementer circuit that performs an adjustment to the preliminary decimal quotient to produce a biased decimal quotient,
- wherein the decimal multiplier circuit further multiplies the divisor by the biased decimal quotient to generate signals for rounding and correction;
- and
- a processing circuit to output a decimal floating-point quotient based on the biased decimal quotient.
Dependencies are inferred from the claim text.