# US 7,466,922 B2 · Flexible control and status architecture for optical modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,922 B2 - Document ID: US7466922B2 - Status: Granted - Kind: B2 - Application number: 11/167,410 - Filed: 2005-06-27 - Published: 2005-12-29 - Granted: 2008-12-16 - Earliest claimed: 2004-06-28 - Assignees: JDS Uniphase Corporation - Inventors: Jay J. Pierce; Darrel Kanagy; David Schneider; Christopher A. Zuhlke - Web page: https://patentgrep.com/patent/US7466922B2 ## CPC - H04B 10/40: Transceivers - H04B: TRANSMISSION ## Abstract The invention relates to optoelectronic modules for generating and/or receiving optical signals for use in fiber-optic communication systems, such as optical transponders or transceivers, having a reconfigurable control and status (C&S) interface with a host device. The optoelectronic module includes an electrical multi-pin host connector having a plurality of pins for communicating a plurality of digital C&S signals between the host and the module, functional hardware responsive to the digital control signals and comprising sensing means for generating digital status signals, and processing means formed by an FPGA and a processor for processing the digital C&S signals. The FPGA is disposed in communications paths between the host connector on one side, and the functional hardware and the processor on the other side, and programmed for routing each of the discrete C&S signals between the C&S pins of the host connector and the processor, and between the C&S pins and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions. ## Claims ### Claim 1 An optoelectronic module for transmitting or receiving optical signals through a fiber-optic link, the module comprising: an electrical I/O port for connecting the module to an external host device, comprising first connection means for providing discrete electrical connections therebetween for a plurality of digital control and status (C&S) signals, said plurality of digital C&S signals comprising digital control signals and digital status signals; an optical port for connecting to the fiber-optic link; functional hardware responsive to the digital control signals, comprising: a) one of electro-optic generating means for generating an output optical signal, and opto-electronic receiving means for receiving an input optical signal and for converting thereof into a received electrical signal; and, b) sensing means for providing status information and for generating the digital status signals; processing means for processing the plurality of digital control and status signals, the processing means comprising a processor and an FPGA; electrical circuitry for establishing communication paths between the electrical I/O port of the module, the processing means and the functional hardware; wherein the FPGA is disposed in the communication paths between said first connection means on one side, and the functional hardware and the processor on the other side, and programmed with an instruction set for routing each of the digital control and status signals between the first connection means and the processor, and the first connection means and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions. ### Claim 2 (depends on 1) A module according to claim 1, wherein the FPGA has a plurality of ports electrically connected to the first connection means by a plurality of electrical connection leads for communicating the plurality of digital C&S signals therebetween. ### Claim 3 (depends on 2) A module according to claim 2, wherein the I/O electrical port comprises a multi-pin connector, and wherein the first connection means comprises a first plurality of pins. ### Claim 4 (depends on 3) A module according to claim 3, wherein each of the digital C&S signals is associated with a different pin from the first plurality of pins, said pin electrically connected to one of the ports of the FPGA for routing the digital C&S signals according to the FPGA instruction set. ### Claim 5 (depends on 2) A module according to claim 2, wherein a total number of the FPGA ports connected to the first connecting means exceeds a total number of the C&S signals routed by the FPGA. ### Claim 6 (depends on 1) A module according to claim 1, wherein the FPGA is programmed for routing at least one of the digital control signals without substantial modification thereof to the processor. ### Claim 7 (depends on 1) A module according to claim 1, wherein the communication path between the FPGA and the processor comprises at least one of: a plurality of discrete electrical leads, a parallel bus and a serial bus. ### Claim 8 (depends on 1) A module according to claim 1, wherein the processor is programmed to modify at least one of the control signals received from the FPGA for forming a modified control signal, and for communicating the modified control signal back to the FPGA for further routing thereof to the functional hardware. ### Claim 9 (depends on 1) A module according to claim 1, wherein the FPGA is programmed for processing at least one of the control signals for forming a modified control signal, and for routing said modified control signal to the functional hardware. ### Claim 10 (depends on 1) A module according to claim 1, wherein the digital status signals comprise a status signal generated by the processor from an output signal provided by the sensing means, and routed by the FPGA to the first connection means. ### Claim 11 (depends on 1) A module according to claim 1, wherein the digital status signals comprise one or more digital status signals generated by the sensing means and sent therefrom bypassing the processor directly to the FPGA, for routing said one or more digital status signals to the first connection means. ### Claim 12 (depends on 11) A module according to claim 11, wherein at least one of said one or more digital status signals is routed by the FPGA to the processor for performing at least one action selected from the group of actions consisting of: processing said signals, and communicating said signals to the host device via a serial bus. ### Claim 13 (depends on 1) A module according to claim 1, wherein the functional hardware is provisioned to provide first information pertinent to one of the digital status signals to the processor for processing therein, and second information pertinent to said digital status signal to the FPGA bypassing the processor, and wherein the FPGA is programmable to form said digital status signal for outputting thereof via the electrical I/O port based upon any one of the first information, the second information, and a combination thereof. ### Claim 14 (depends on 1) A module according to claim 1, wherein the FPGA is programmed to generate at least one digital control signal in response to at least one of the digital status signals. ### Claim 15 (depends on 3) A module according to claim 3, wherein the multi-pin connector is a 300-pin MSA connector. ### Claim 16 (depends on 3) A module according to claim 3 for transmitting and receiving optical signals through the fiber-optic link, wherein the functional hardware comprises: electro-optic generatng means for generating an output optical signal; opto-electronic receiving means for receiving an input optical signal and for converting thereof into a received electrical signal; an electrical multiplexer for multiplexing a plurality of input electrical data signals received from the host device into a multiplexed electrical data signal for communicating thereof to the electro-optic generating means; and, an electrical de-multiplexer for de-multiplexing an electrical data signal provided by the opto-electronic receiver into a plurality of parallel output electrical data signals for communicating thereof to the host device. ### Claim 17 (depends on 16) A module according to claim 16, wherein the sensing means include one or more sensors coupled to the electrical multiplexer, and one or more sensors coupled to the electrical de-multiplexer, for generating digital status signals for passing thereof to the FPGA. ### Claim 18 An optoelectronic module for transmitting or receiving optical signals through a fiber-optic link, the module comprising: an electrical I/O port for connecting the module to an external host device, comprising first connection means for providing discrete electrical connections therebetween for a plurality of digital control and status (C&S) signals, said plurality of digital C&S signals comprising digital control signals and digital status signals; an optical port for connecting to the fiber-optic link; functional hardware responsive to the digital control signals, comprising: a) one of an electro-optic generating means for generating an output optical signal, and an optoelectronic receiving means for receiving an input optical signal and for converting thereof into a received electrical signal; and, b) a sensing means for providing status information and for generating the digital status signals; a processing means for processing the plurality of digital control and status signals, the processing means comprising an FPGA and a processor programmed therewithin; electrical circuitry for establishing communication paths between the electrical I/O port of the module, the processing means and the functional hardware; wherein the FPGA is disposed in the communication paths between the electrical I/O port of the module and the functional hardware, and programmed with an instruction set for routing each of the discrete digital control and status signals between the first connection means and the processor, and the first connection means and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions.