# US 7,466,782 B1 · Methods, apparatus and computer program products for determining the timing of bits based on frequency error

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- Number: US 7,466,782 B1
- Document ID: US7466782B1
- Status: Granted
- Kind: B1
- Application number: 10/873,103
- Filed: 2004-06-21
- Granted: 2008-12-16
- Earliest claimed: 2004-02-05
- Assignees: Maxtor Corporation
- Inventors: Ara Patapoutian
- Web page: https://patentgrep.com/patent/US7466782B1

## CPC

- G11B 20/1403: {characterised by the use of two levels}
- G11B 20/10009: {Improvement or modification of read or write signals}
- G11B 20/10037: {A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof}
- G11B 20/10046: {filtering or equalising, e.g. setting the tap weights of an FIR filter}
- G11B 20/10222: {clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation (dedicated sync patterns in the modulation code G11B20/1403)}
- G11B 20/10425: {by counting out-of-lock events of a PLL}
- G11B 20/10481: {optimisation methods}
- G11B 5/09: Digital recording
- G11B 2220/2516: Hard disks
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)

## Abstract

Determining timing for bits in sampled data includes determining a bit error in the sampled data, determining a phase error in the sampled data, determining a frequency error of the sampled data based on the bit error and based on the phase error, and determining the timing for bits in the sampled data based on the determined frequency error.

## Claims

### Claim 1

A method of determining timing for bits in sampled data, the method comprising:
determining a bit error in the sampled data;
determining a phase error in the sampled data;
determining a frequency error of the sampled data based on combining the bit error, the phase error, and a number of bits between first and second locations in the sampled data to determine the frequency error; and
determining the timing for bits in the sampled data based on the determined frequency error.

### Claim 2 (depends on 1)

The method of claim 1, wherein determining a frequency error comprises:
adding the bit error and the phase error to generate a result; and
multiplying the result by an inverse of the number of bits between the first and second locations in the sampled data to determine the frequency error.

### Claim 3 (depends on 1)

The method of claim 1, wherein determining a bit error comprises:
detecting a number of bits between the first and second locations in the sampled data; and
comparing the detected number of bits and a predetermined number of bits between the first and second locations to determine the bit error.

### Claim 4 (depends on 3)

The method of claim 3, wherein the sampled data comprises first mark bits and second mark bits, wherein the first location corresponds to a location of the first mark bits, wherein the second location corresponds to a location of the second mark bits, and wherein the predetermined number of bits is based on a predetermined number of bits between the first mark bits and the second mark bits.

### Claim 5 (depends on 4)

The method of claim 4, wherein detecting a number of bits between the first and second locations in the sampled data comprises:
detecting the first mark bits;
detecting the second mark bits; and
determining the number of bits between the first and second mark bits.

### Claim 6 (depends on 5)

The method of claim 5, wherein at least one of detecting the first mark bits and detecting the second mark bits comprises searching the sampled data for at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 7 (depends on 5)

The method of claim 5, wherein at least one of detecting the first mark bits and detecting the second mark bits comprises:
generating synchronous samples from the sampled data;
filtering the synchronous samples to generate filtered samples; and
comparing the filtered samples to a threshold value to detect at least one of the first and second mark bits.

### Claim 8 (depends on 7)

The method of claim 7, wherein filtering the synchronous samples to generate filtered samples comprises selecting filter coefficients for filtering the synchronous samples based on at least one of the first and second mark bits.

### Claim 9 (depends on 8)

The method of claim 8, wherein selecting filter coefficients comprises selecting the filter coefficients based on at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 10 (depends on 8)

The method of claim 8, wherein filtering the synchronous samples comprises finite-impulse response filtering the synchronous samples to generate the filtered samples, and further comprising selecting filter coefficients for the finite-impulse response filtering based on at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 11 (depends on 5)

The method of claim 5, wherein at least one of detecting the first mark bits and detecting the second mark bits comprises:
filtering the sampled data to generate filtered samples; and
comparing the filtered samples to a threshold value to detect at least one of the first and second mark bits.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
filtering the sampled data to generate filtered samples using filter coefficients that are generated based on the phase error in the sampled data; and
comparing the filtered samples to a threshold value to detect at least one of the first and second mark bits in the filtered samples.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
filtering the sampled data comprises finite-impulse response filtering the sampled data to generate the filtered samples using filter coefficients that are generated based on the phase error in the sampled data.

### Claim 14 (depends on 1)

The method of claim 1, wherein the sampled data comprises first phase bits and second phase bits, and wherein determining a phase error in the sampled data comprises:
determining a first phase based on the first phase bits;
determining a second phase based on the second phase bits; and
determining the phase error based on the first and second phases.

### Claim 15 (depends on 1)

The method of claim 1, wherein determining the timing for bits in the sampled data based on the determined frequency error comprises filtering a timing error signal based on the frequency error and a phase error between bit decisions and synchronous data to determine the timing for bits in the sampled data.

### Claim 16 (depends on 1)

The method of claim 1, further comprising:
reading data from a storage surface of a data storage disk to generate read data, wherein the read data includes first mark bits, second mark bits, and a predetermined number of bits between the first and second mark bits; and
sampling the read data to generate the sampled data, and
wherein determining a bit error in the sampled data comprises detecting the first mark bits, detecting the second mark bits, determining a number of bits between the first and second mark bits, and determining the bit error based on the determined number of bits and the predetermined number of bits,
wherein determining a frequency error comprises combining the bit error, the phase error, and at least one of the determined number of bits between the first and second mark bits and the predetermined number of bits between the first and second mark bits.

### Claim 17 (depends on 16)

The method of claim 16, wherein determining a frequency error comprises:
adding the bit error and the phase error to generate a result; and
multiplying the result by an inverse of the predetermined number of bits between the first and second mark bits to determine the frequency error.

### Claim 18 (depends on 1)

The method of claim 1, further comprising responding to the determined bit timing by adjusting phase of a clock signal that is used to sample asynchronous data read from a disk to generate the sampled data.

### Claim 19

An apparatus for determining timing for bits in sampled data, the apparatus comprising:
a frequency error estimator that is configured to determine a bit error in the sampled data, configured to determine a phase error in the sampled data, and configured to determine a frequency error of the sample data based on a combination of the bit error, the phase error, and a number of bits between first and second locations in the sampled data; and
a timing estimator that is configured to determine the timing for bits in the sampled data based on the determined frequency error.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the frequency error estimator is configured to add the bit error and the phase error to generate a result, and configured to multiply the result by an inverse of the number of bits between the first and second locations in the sampled data to determine the frequency error.

### Claim 21 (depends on 19)

The apparatus of claim 19, wherein the frequency error estimator is configured to detect a number of bits between the first and second locations in the sampled data, and configured to comparing the detected number of bits and a predetermined number of bits between the first and second locations to determine the bit error.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the sampled data comprises first mark bits that correspond to the first location in the sampled data and second mark bits that correspond to the second location in the sampled data, wherein the frequency error estimator is configured to detect the first and second mark bits in the sampled data, and is configured to detect the number of bits between the first and second mark bits.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein the frequency error estimator is configured to search the sampled data for at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 24 (depends on 22)

The apparatus of claim 22, wherein the frequency error estimator is configured to generate synchronous samples from the sampled data, configured to filter the synchronous samples to generate filtered samples, and configured to compare the filtered samples to a threshold value to detect at least one of the first and second mark bits.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the frequency error estimator comprises a mark bit detector, wherein the mark bit detector comprises:
a zero phase start circuit that generates phase information based on the sampled data;
an interpolated timing recover circuit that generates synchronous sampled data based on the sampled data and the phase information;
a filter that is configured to filter the sampled data based on filter coefficients to generate filtered sampled data, wherein the filter coefficients are based on at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits; and
a comparator that is configured to compare the filtered sampled data and a threshold value to generate an indication of at least one of the first and second mark bits.

### Claim 26 (depends on 24)

The apparatus of claim 24, wherein the frequency error estimator comprises a filter that filters the sampled data based on filter coefficients, wherein the filter coefficients are based on at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein the filter comprises a finite-impulse response filter with filter coefficients that are based on at least one predetermined symbol sequence that corresponds to at least one of the first and second mark bits.

### Claim 28 (depends on 24)

The apparatus of claim 24, wherein the frequency error estimator comprises a mark bit detector, wherein the mark bit detector comprises:
a zero phase start circuit that generates phase information based on the sampled data;
a filter coefficient generator that is configured to generate filter coefficients based on the phase information;
a filter that is configured to filter the sampled data based on the filter coefficients to generate filtered sampled data; and
a comparator that is configured to compare the filtered sampled data and a threshold value to generate an indication of at least one of the first and second mark bits.

### Claim 29 (depends on 19)

The apparatus of claim 19, wherein the frequency error estimator is configured to filter the sampled data based on filter coefficients to generate filtered sampled data, wherein the filter coefficients are generated based on the phase error in the sampled data, and wherein the frequency error estimator is configured to compare the filtered sampled data to a threshold value to detect at least one of first and second mark bits in the filtered sampled data.

### Claim 30 (depends on 19)

The apparatus of claim 19, wherein the timing estimator is configured to filter a timing error signal based on the frequency error and the phase error in the sampled data to determine the timing for bits in the sampled data.

### Claim 31

A computer program product for determining timing for bits in sampled data, the computer program product comprising program code embodied in a computer-readable storage medium, the computer program code comprising:
program code that is configured to determine a bit error in the sampled data;
program code that is configured to determine a phase error in the sampled data;
program code that is configured to determine a frequency error of the sampled data based on combining the bit error, the phase error, and a number of bits between first and second locations in the sampled data to determine the frequency error; and
program code that is configured to determine the timing for bits in the sampled data based on the determined frequency error.

### Claim 32 (depends on 31)

The computer program product of claim 31, further comprising:
program code that is configured to add the bit error and the phase error to generate a result; and
program code that is configured to multiply the result by an inverse of the number of bits between the first and second locations in the sampled data to determine the frequency error.

### Claim 33 (depends on 31)

The computer program product of claim 31, further comprising:
program code that is configured to detect a number of bits between the first and second locations in the sampled data; and
program code that is configured to compare the detected number of bits and a predetermined number of bits between the first and second locations to determine the bit error.