# US 7,466,709 B1 · ATM switching equipment having a switching network

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- Number: US 7,466,709 B1
- Document ID: US7466709B1
- Status: Granted
- Kind: B1
- Application number: 09/826,357
- Filed: 2000-06-14
- Granted: 2008-12-16
- Earliest claimed: 1999-06-14
- Assignees: Nokia Siemens Networks Oy
- Inventors: Ralf Haferbeck; Stefan Schneeberger
- Web page: https://patentgrep.com/patent/US7466709B1

## CPC

- H04L 49/309: {Header conversion, routing tables or routing tags}
- H04L 49/3081: {ATM peripheral units, e.g. policing, insertion or extraction}
- H04Q 11/0478: {Provisions for broadband connections}
- H04L 2012/5656: {using the AAL2}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

An ATM switching equipment is provided comprising a switching network (ASN) and at least one server switching unit (SSC). The server switching unit (SSC) contains an AAL2 switcher (ASW) that is configured for simultaneous processing of a maximum plurality (m) of incoming connections. An AAL2 routing list (RL1 . . . RLm) is provided for each of these connections, and a microprocessor (MPR) is configured to limit the allowable value range for VPI/VCI values in the header of the ATM cells according to the plurality of AAL2 routing lists, so that only the corresponding VPI/VCI coding bits are taken into consideration at an interface to the switching network.

## Claims

### Claim 1

An ATM switching equipment comprising:
a switching network;
an input interface unit including an input processing unit;
an output interface unit including an output processing unit;
a microprocessor;
a server switching unit comprising:
an AAL2 switcher that is connected to the switching network via a first interface;
an input processing unit to which said AAL2 switcher is connected; and
an output processing unit to which said AAL2 switcher is connected;
said switching equipment being configured to write a new VPI/VCI information, including VP/VCI bits, for a further connecting section into cells of arriving data streams upon utilization of routing tables,
said AAL2 switcher being configured for simultaneous processing of a maximum plurality of incoming connections, an AAL2 routing list being provided for each of said incoming connections;
said AAL2 switcher being connected to said switching network without requiring recognition of all VPINCI bits in the AAL2 switcher; and
said microprocessor limiting the number of bits representing VPINCI bits from among VPI/VCI bits transmitted in a header of ATM cells to be interpreted according to a number of ATM connections available for processing, as indicated in said AAL2 routing lists, so that said first interface considers corresponding VPI/VCI bits.

### Claim 2 (depends on 1)

The ATM switching equipment according to claim 1, wherein said first interface is a UTOPIA interface.

### Claim 3 (depends on 1)

The ATM switching equipment according to claim 1, wherein a single virtual path is established between said switching network and said server switching unit.

### Claim 4 (depends on 1)

The ATM switching equipment according to claim 1, further comprising:
buffer memories which are allocated to said routing lists; and
a section of an AAL2 packet of an ATM cell being writable into said buffer memories, said section being readable from said buffer memories when processing a next-successive ATM cell and for completion of a remainder of said AAL2 packet.

### Claim 5

An ATM switching apparatus, comprising:
a microprocessor; and
a server switching unit, comprising:
an input processing unit;
an AAL2 switcher that is coupled to the input processing unit, and is further coupled to a switching network via a first interface;
an output processing unit, coupled to the AAL2 switcher, wherein the AAL2 switcher simultaneously processes a maximum plurality of incoming connections, and wherein an AAL2 routing list is provided for each of the incoming connections;
wherein the ATM switching apparatus writes new VPI/VCI information including VPI/VCI bits for a further connecting section into cells of arriving data streams using routing tables, and wherein the microprocessor limits the number of bits representing VPI/VCI bits from among VPI/VCI bits transmitted in a header of ATM cells to be interpreted according to a number of ATM connections available for processing as indicated in the AAL2 routing lists, so that the first interface considers corresponding VPI/VCI bits.