# US 7,466,614 B2 · Sense amplifier for non-volatile memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,466,614 B2
- Document ID: US7466614B2
- Status: Granted
- Kind: B2
- Application number: 11/546,122
- Filed: 2006-10-10
- Published: 2008-04-10
- Granted: 2008-12-16
- Earliest claimed: 2006-10-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chin-Huang Wang
- Web page: https://patentgrep.com/patent/US7466614B2

## CPC

- G11C 7/067: {Single-ended amplifiers}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A sense amplifier comprising a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit, a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal, a latch control circuit for providing control of a latch circuit based on the sense signal, the precharge signal and the logical inverse of the sense output signal, wherein when the sense signal is read, the latch control circuit provides one or more predetermined signals to the latch circuit to latch the sense signal to a logical level.

## Claims

### Claim 1

A sense amplifier comprising:
a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit;
a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal; and
a latch control circuit including a plurality of inverters and a NOR gate for selectively controlling a pull-up device and a pull-down device to maintain the sense signal at a predetermined voltage level in response to the sense signal, the precharge signal and the logical inverse of the sense output signal.

### Claim 2 (depends on 1)

The sense amplifier of claim 1, wherein the sense output circuit comprises:
a first inverter for receiving the sense signal; and
a second inverter for controlling a third inverter based on an output of the first inverter,
wherein an output of the third inverter is the sense output signal and an input to the third inverter is the logical inverse of the sense output signal.

### Claim 3 (depends on 2)

The sense amplifier of claim 2, wherein the latch control circuit comprises:
a fourth inverter for receiving the sense signal;
a fifth inverter for controlling a sixth inverter based on the output of the fourth inverter; and
a NOR gate for providing a first control signal to the latch circuit based on the logical inverse of the sense output signal and the precharge signal,
wherein the output of the sixth inverter provides a second control signal to the latch circuit.

### Claim 4 (depends on 3)

The sense amplifier of claim 3, wherein the threshold voltage of the fourth inverter is higher than the threshold voltage of the first inverter.

### Claim 5 (depends on 4)

The sense amplifier of claim 4, wherein the latch circuit comprises a pull-up transistor and a pull-down transistor with the sense signal coupled to the drain ends thereof.

### Claim 6 (depends on 1)

The sense amplifier of claim 1 further comprising:
a precharge circuit for precharging the sense output circuit in response to the precharge signal and the sense enable signal.

### Claim 7 (depends on 6)

The sense amplifier of claim 6, wherein the memory cell is a flash memory.

### Claim 8

A sense amplifier comprising:
a first inverter having an input connected to a sense node of a memory circuit;
a second inverter whose input is connected to the output of the first inverter;
a third inverter whose input is connected to the output of the second inverter and whose output is connected to a charge control circuit;
a fourth inverter whose input is connected to the sense node;
a fifth inverter whose input is connected to the output of the fourth inverter;
a sixth inverter whose input is connected to the output of the fifth inverter and whose output is connected to the gate of a PMOS device having its source connected to a positive supply voltage and its drain connected to the sense node; and
a NOR gate having one input connected to the output of the second inverter, a second input connected to the output of a charge control circuit and an output connected to the gate of an NMOS device whose drain is connected to the sense line and whose source is connected to a negative supply (GND).

### Claim 9 (depends on 8)

The sense amplifier of claim 8, wherein the threshold voltage for the fourth inverter is higher than the threshold voltage for the first inverter.

### Claim 10 (depends on 9)

The sense amplifier of claim 9, wherein the memory cell is a flash memory.

### Claim 11

A method for sensing the value of a memory cell comprising:
receiving the sense signal from the memory cell;
combining the sense signal with a precharge signal to generate a pull-up signal and a pull-down signal;
applying the pull-up signal to a pull-up transistor connected between the sense signal and a positive supply voltage; and
applying the pull-down signal to a pull-down transistor connected between the sense signal and a negative supply voltage,
wherein when the sense signal changes during a memory read, feedback will be applied to the sense signal latching it to a logic level.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the pull-up transistor is a PMOS device whose source is connected to the positive supply voltage, whose drain is connected to the sense signal and whose gate is connected to the pull-up signal;
the pull-down transistor is an NMOS device whose drain is connected to the sense line, whose source is connected to the negative supply and whose gate is connected to the pull-down signal.

### Claim 13 (depends on 11)

The method of claim 11, wherein the step of receiving the sense signal further comprises:
receiving the sense signal into a first inverter; and
receiving the sense signal into a second inverter,
wherein the threshold voltage of the first inverter is lower than the threshold voltage of the second inverter.

### Claim 14 (depends on 13)

The method of claim 13, wherein the pull-down signal is generated by applying the precharge signal to a first input of a NOR gate and applying the logical inverse of a sense output to a second input of a NOR gate, whereby the output of the NOR gate is the pull-down signal.

### Claim 15 (depends on 13)

The method of claim 13, wherein the pull-up signal is generated by:
applying the output of the second inverter to the input of a third inverter; and
applying the output of the third inverter to yet a fourth inverter,
wherein the output of the fourth inverter is the pull-up signal.

### Claim 16 (depends on 14)

The method of claim 14, wherein the memory cell is a flash memory.