# US 7,466,609 B2 · Semiconductor memory device and semiconductor memory device control method

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- Number: US 7,466,609 B2
- Document ID: US7466609B2
- Status: Granted
- Kind: B2
- Application number: 11/882,230
- Filed: 2007-07-31
- Published: 2007-12-06
- Granted: 2008-12-16
- Earliest claimed: 2002-03-15
- Assignees: NEC Electronics Corporation
- Inventors: Hiroyuki Takahashi; Takuya Hirota; Atsushi Nakagawa
- Web page: https://patentgrep.com/patent/US7466609B2

## CPC

- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- H03K 5/133: using a chain of active delay devices
- G11C 2207/2227: Standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arranged in an array form;
a voltage step down circuit that receives a power supply voltage and outputs a step down voltage that is lower than said power supply voltage;
a voltage step up circuit that receives said step down voltage and outputs a step up voltage;
a peripheral circuit outputting a word line voltage and receiving said step up voltage and said power supply voltage; and
a delay circuit being driven by said step down voltage, said delay circuit having a characteristic in which a delay time thereof decreases more when the voltage provided to the delay circuit is low than when the voltage provided to the delay circuit is high.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1,
wherein said peripheral circuit comprises;
a sense amplifier amplifying a high level voltage of a selected bit line to said power supply voltage; and
a word line driving circuit driving a selected word line by the step up voltage.