# US 7,466,605 B2 · Semiconductor device and control method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,605 B2 - Document ID: US7466605B2 - Status: Granted - Kind: B2 - Application number: 11/360,091 - Filed: 2006-02-22 - Published: 2006-10-26 - Granted: 2008-12-16 - Earliest claimed: 2005-02-23 - Assignees: Spansion LLC - Inventors: Atsushi Shimizu; Hiroki Murakami - Web page: https://patentgrep.com/patent/US7466605B2 ## CPC - G11C 16/30: Power supply circuits - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/12: Programming voltage switching circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A non-volatile semiconductor device provides a pull-up transistor (M1) for a word line drive which can be downsized. The semiconductor device includes a first decoder (109) including a pull-up transistor (M1) selecting and driving a word line (P2WL) connected to memory cells, a first voltage generating circuit (102) generating a first voltage applied to a source terminal of the pull-up transistor (M1), a second voltage generating circuit (105) generating a second voltage that is applied to a gate terminal of the pull-up transistor (M1), is the second voltage higher than the first voltage, sectors including the memory cells, a vertical word line (VWL) connecting the sectors in a vertical direction and carrying the first voltage to the source terminal of the pull-up transistor (M1), a global word line (GWL) connecting the sectors in a lateral direction and carrying the second voltage to the gate terminal of the pull-up transistor (M1), a second decoder (108) selecting and driving the global word line (GWL), and a third decoder (104) selecting and driving the vertical word line (VWL). ## Claims ### Claim 1 A nonvolatile semiconductor memory device comprising: a plurality of non-volatile memory cells divided into sectors; a first decoder including a pull-up transistor for selecting and driving a word line connected to the plurality of non-volatile memory cells; a first voltage generating circuit generating a first voltage applied to a source terminal of the pull-up transistor; a vertical word line connecting the sectors in a vertical direction and carrying the first voltage from the first voltage generating circuit to the source terminal of the pull-up transistor; a second voltage generating circuit generating a second voltage that is applied to a gate terminal of the pull-up transistor and is higher than the first voltage; a global word line connecting the sectors in a lateral direction and carrying the second voltage from the second voltage generating circuit to the gate terminal of the pull-up transistor; a second decoder selecting and driving the global word line; and a third decoder selecting and driving the vertical word line. ### Claim 2 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, further comprising a switch circuit selectively connecting the first voltage generating circuit to the third decoder. ### Claim 3 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, further comprising a switch circuit selectively connecting the second voltage generating circuit to the second decoder. ### Claim 4 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first voltage generating circuit comprises a first reading boost circuit generating a first reading voltage used during reading and a first writing boost circuit generating a first writing voltage used during writing. ### Claim 5 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, wherein the second voltage generating circuit generates a gate voltage applied to a select transistor provided on a drain side of the memory cells. ### Claim 6 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, wherein the second voltage generating circuit generates the second voltage at a same time as the first voltage generating circuit generates the first voltage. ### Claim 7 A method for controlling a nonvolatile semiconductor memory device comprising the steps of: generating, by a first voltage generating circuit, a first voltage applied to a source terminal of a pull-up transistor selecting and driving a word line connected to nonvolatile memory cells, wherein the first voltage generating circuit generates a first reading voltage for use during reading and generates a first writing voltage for use during writing; and generating, by a second voltage generating circuit, a second voltage that is applied to a gate terminal of the pull-up transistor and is higher than the first voltage. ### Claim 8 (depends on 7) The method as claimed in claim 7, wherein the step of generating the second voltage comprises the step of generating a second reading voltage for use during reading and generating a second writing voltage for use during writing. ### Claim 9 (depends on 7) The method as claimed in claim 7, wherein the step of generating the second voltage generates the second voltage at a same time as the first voltage is generated. ### Claim 10 (depends on 1) The nonvolatile semiconductor memory device as claimed in claim 1, wherein the second voltage generating circuit comprises a reading boost circuit generating a reading voltage used during reading and a writing boost circuit generating a writing voltage used during writing. ### Claim 11 (depends on 4) The nonvolatile semiconductor memory device as claimed in claim 4, wherein the second voltage generating circuit comprises a second reading boost circuit generating a second reading voltage used during reading and a second writing boost circuit generating a second writing voltage used during writing. ### Claim 12 A method for controlling a nonvolatile semiconductor memory device comprising the steps of: generating, by a first voltage generating circuit, a first voltage applied to a source terminal of a pull-up transistor selecting and driving a word line connected to nonvolatile memory cells; and generating, by a second voltage generating circuit, a second voltage that is applied to a gate terminal of the pull-up transistor and is higher than the first voltage, wherein the second voltage generating circuit generates a reading voltage for use during reading and generates a writing voltage for use during writing.