NAND flash memory device and copyback program method for same

An error detection method for a NAND flash memory device comprising:

• inputting data in a cell array of the flash memory device;
• reading data from the cell array and storing the data in a page buffer;
• detecting errors that occurred while reading data from the cell array and storing the data in the page buffer while concurrently performing a copyback program operation;
• confirming whether detecting errors has ended;
• and
• performing a program verify operation;
• wherein the flash memory device including the cell array and page buffer is fabricated on a semiconductor chip;
• and
• wherein detecting the errors is performed internally in the flash memory device on the semiconductor chip.

An error detection method for a NAND flash memory device comprising:

• inputting data in a cell array of the flash memory device;
• reading data from the cell array and storing the data in a page buffer;
• detecting errors that occurred while reading data from the cell array and storing the data in the page buffer while concurrently performing a copyback program operation;
• confirming whether detecting errors has ended;
• and
• performing a program verify operation;
• wherein detecting the errors is performed internally in the flash memory device;
• and
• wherein performing the copyback program operation comprises:
• generating a high voltage and setting up a bit line;
• applying the high voltage to a selected word line;
• and
• recovering after the copyback program operation.

A NAND flash memory device comprising:

• a cell array configured to store data;
• a page buffer configured to copyback read the data;
• an error detector configured to detect errors during a copyback program operation;
• and
• a control device configured to control the error detector such that error detection ends before a program verify operation is performed;
• wherein the cell array, page buffer and error detector are fabricated on the same semiconductor chip.

A NAND flash memory device comprising:

• a cell array structured to store data and a first parity for the data;
• a page buffer structured to copyback read the data and the first parity;
• a first parity generator structured to receive the data stored in the page buffer and to generate a second parity in synchronization with a first clock signal during a copyback program operation;
• a comparator that is structured to compare the first and second parities and to generate a detection signal in synchronization with a second clock signal;
• and
• a control device structured to control the first and second clock signals and to generate the detection signal before a program verify operation begins.

A copyback program method for a NAND flash memory device comprising:

• reading data stored in a cell array of the flash memory device;
• detecting errors that occur during reading of the data;
• copyback programming the data read from the cell array according to a result of detecting errors;
• and
• generating a high voltage and setting up a bit line concurrently with detecting errors.

A NAND flash memory device comprising:

• a cell array configured to store data;
• a page buffer configured to copyback read the data;
• an error detector configured to detect errors that occur during a copyback read operation;
• a control device responsive to the error detector and configured to control the page buffer and the error detector to copyback program the data stored in the page buffer;
• and
• a high voltage generator circuit configured to set up a bit line concurrently with detecting errors.

A NAND flash memory device comprising:

• a cell array configured to store data and a first parity for the data;
• a page buffer configured to copyback read the data and the first parity;
• a first parity generator configured to receive the data stored in the page buffer and to generate a second parity;
• a comparator configured to compare the first and second parities and to generate a detection signal;
• and
• a control device configured to control the page buffer, the first parity generator, and the comparator to copyback program the data stored in the page buffer in response to the detection signal;
• wherein the cell array comprises:
• a main cell array configured to store the data;
• and
• a redundancy cell array configured to store the first parity.

A NAND flash memory device comprising:

• a cell array configured to store data and a first parity for the data;
• a page buffer configured to copyback read the data and the first parity;
• a first parity generator configured to receive the data stored in the page buffer and to generate a second parity;
• a comparator configured to compare the first and second parities and to generate a detection signal;
• a control device configured to control the page buffer, the first parity generator, and the comparator to copyback program the data stored in the page buffer in response to the detection signal;
• and
• a second parity generator configured to generate the first parity while the data is input into the cell array.