# US 7,466,586 B2 · Diode-based capacitor memory and its applications

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- Number: US 7,466,586 B2
- Document ID: US7466586B2
- Status: Granted
- Kind: B2
- Application number: 11/306,756
- Filed: 2006-01-10
- Published: 2007-06-14
- Granted: 2008-12-16
- Earliest claimed: 2005-12-08
- Inventors: Juhan Kim
- Web page: https://patentgrep.com/patent/US7466586B2

## CPC

- G11C 11/24: using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40)
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/106: {Data output latches}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/22: using ferroelectric elements
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4067: for memory cells of the bipolar type
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4094: Bit-line management or control circuits
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 15/043: {using capacitive charge storage elements}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/10: DRAM devices comprising bipolar components
- H10B 99/14: {comprising memory cells that only have passive resistors or passive capacitors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2211/4016: Memory devices with silicon-on-insulator cells
- G11C 2213/72: Array wherein the access device being a diode
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Diode-based capacitor memory uses relatively small capacitor, and uses a diode as an access device instead of MOS transistor, wherein the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to the first plate of capacitor which serves as a storage node, the third terminal is floating, the fourth terminal is connected to a bit line, wherein the capacitor is formed between the first plate and the second plate, and a plate line is connected to the second plate, during write the storage node is coupled or not, depending on the state of the diode by changing the plate line, during read the diode serves as a sense amplifier as well to detect the storage node voltage whether it is forward bias or not, in this manner the capacitor does not drive heavily loaded bit line directly, instead, it drives lightly loaded second terminal, and then the diode sends binary results to a data latch including a current mirror which repeats the amount of current that the memory cell flows, and the word line is de-asserted to cut off the holding current during standby, in addition its applications are extended to single port and content addressable memory. Furthermore, cell structures are devised on the bulk or SOI wafer.

## Claims

### Claim 1

A random access memory, comprising:
capacitor as a storage element, wherein is formed by an insulator(s) between a first plate and a second plate; and
diode as an access device, wherein includes four terminals, a first terminal is p-type, a second terminal is n-type, a third terminal is p-type, a fourth terminal is n-type, the first terminal is connected to a word line, the second terminal is connected to the first plate of the capacitor which serves as a storage node, the third terminal is floating, and the fourth terminal is connected to a bit line to write or read data; and plate line is connected to the second plate of the capacitor which couples to the first plate of the capacitor, and the word line is turned off to cut holding current of the diode during standby; and
write sequence, wherein the word line is raised to high level first, and then the plate line is lowered to ground level to clear previous data, then the bit line is asserted, after then the plate line is returned to high level, but the storage node is not coupled by returning the plate line because the diode is in on state when write data is logic high, otherwise the storage node is coupled to higher than logic high level because the diode is in off state when the write data is logic low, after then the word line is de-asserted to ground level, and finally the bit line is de-asserted to ground level; and
read sequence, wherein the word line is asserted to high level first, which enables the diode to detect the storage node voltage whether it is forward bias or not, thus the diode is turned on when stored data is logic high otherwise it is not turned on when the stored data is logic low, and then the diode transfers charges to a data latch when the stored data is logic high, otherwise it does not when the stored data is logic low; and
data latch including pull-down transistor, current mirror and two inverter-type latch, wherein the pull-down transistor is turned on by the diode when the stored data is logic high, at the same time the current mirror repeats the current and changes latch node from a pre-charge state, after then the latch node is sustained by the latch which the latch node becomes input of first inverter, and it is also connected to output of second inverter, and input of second inverter is output of first inverter, otherwise the current mirror does not flow current when the stored data is logic low, when read.

### Claim 2 (depends on 1)

The random access memory of claim 1, wherein the first terminal is n-type, the second terminal is p-type, the third terminal is n-type, the fourth terminal is p-type.

### Claim 3 (depends on 2)

The random access memory of claim 2, wherein includes data latch having pull-up transistor, current mirror and two-inverter type latch, which stores binary states from the memory cell depending on the states of diode, turn-on or turn-off, when read.

### Claim 4 (depends on 1)

The random access memory of claim 1, wherein includes insulator, such as silicon dioxide, silicon nitride, Ta2O5, TiO2, Al2O3, TiN/HfO2/TiN(TIT), and Ru/Insulator/TiN(RIT).

### Claim 5 (depends on 1)

The random access memory of claim 1, wherein includes ferroelectric dielectric, such as lead zirconate titanate (PZT), lead lanthanum zirconium titanate (PLZT), barium strontium titanate (BST), and strontium bismuth tantalate (SBT).

### Claim 6 (depends on 1)

The random access memory of claim 1, wherein is formed from silicon diode, germanium diode, or compound semiconductor diode.

### Claim 7 (depends on 1)

The random access memory of claim 1, wherein the fourth terminal uses metal to form metal-semiconductor diode.

### Claim 8 (depends on 1)

The random access memory of claim 1, wherein word line is repeatedly connected to metal shunting lines outside of memory array, in order to reduce sheet resistance.

### Claim 9 (depends on 1)

The random access memory of claim 1, wherein at least one of the terminals is attached to adjacent terminal vertically, such that word line is connected to the upper side of first terminal through contact layer, first terminal is attached to the upper side of second terminal, third terminal is attached to the upper side of second terminal, fourth terminal is attached to the upper side of third terminal, the storage capacitor is formed in on the bottom of diode between the first plate and the second plate by the insulator, the first plate of the capacitor is attached to a lower side of second terminal.

### Claim 10 (depends on 1)

The random access memory of claim 1, wherein word line is connected to the upper side of first terminal through contact layer, first terminal is attached to the upper side of second terminal, second terminal fully or partially surrounds plate to form capacitor with insulator, second terminal is attached to the upper side of third terminal, and third terminal is attached to the upper side of fourth terminal in the bottom.

### Claim 11 (depends on 1)

The random access memory of claim 1, wherein two memory cells are stacked, and share fourth terminal.

### Claim 12 (depends on 1)

The random access memory of claim 1, wherein is formed on the bulk of the wafer.

### Claim 13 (depends on 1)

The random access memory of claim 1, wherein is formed on the SOI wafer.