# US 7,466,250 B2 · Time interleaved analogue/digital conversion device with self adaptive equalisation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,250 B2 - Document ID: US7466250B2 - Status: Granted - Kind: B2 - Application number: 11/620,344 - Filed: 2007-01-05 - Published: 2007-09-06 - Granted: 2008-12-16 - Earliest claimed: 2006-01-06 - Assignees: Thales - Inventors: Philippe Buisson - Web page: https://patentgrep.com/patent/US7466250B2 ## CPC - H03M 1/1019: {by storing a corrected or correction value in a digital look-up table} - H03M 1/1215: {using time-division multiplexing} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract The invention relates to an equalised time interleaved analogue digital conversion device. The analogue digital conversion device comprises a number N of analogue digital converters distributed in N channels. Each analogue digital converter has a sampling frequency N times lower than the required sampling frequency. The digital signal is built up from samples output from each channel. The device comprises a reference channel comprising an analogue digital converter generating samples of the analogue signal. Each filter comprises an equaliser filter. The filter received a digital signal output by the analogue digital converter of the channel on which it is placed. The filter also receives an error signal and outputs a filtered digital signal s(n) corrected for errors deduced from the error signal. The error signal corresponds to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analogue digital converter of the reference channel. In particular, the invention is applicable to analogue digital converters operating at a high clock frequency, typically of the order of one gigahertz. ## Claims ### Claim 1 Analog digital conversion device receiving an analog signal at its input and outputting a digital signal at a required sampling frequency, said device comprising: a number N of analog digital converters distributed in N channels, each a-analog digital converter having a sampling frequency N times lower than the required sampling frequency, said analog digital converters having clock signals controlling their sampling frequency, offset in time from each other by one period of a signal at the required sampling frequency, the digital signal being built up from samples delivered to the output from each channel, said analog digital conversion device comprising a reference channel, said reference channel comprising an analog digital converter generating samples of the analog signal, each channel comprising an equalizer filter, said filter receiving a digital signal at its input output by the analog digital converter on the channel on which it is located and an error signal, said filter outputting a filtered digital signal s(n) corrected for errors deduced from the error signal, the error signal corresponding to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analog digital converter of the reference channel, the coefficients of said filter being adjusted to present the response that best minimizes the error signal. ### Claim 2 (depends on 1) The device according to claim 1, wherein the error signal corresponds to the difference at a given time between firstly the digital signal corrected by both the filter and by an offset correction device and secondly by the digital signal output by the analogue digital converter of the reference channel, said offset correction device outputting an offset error signal Yn., said offset error signal Yn being generated at time n by applying the mathematical relation yn+1=yn+errn*m at time n where errn is the value of the error signal (24) at time n and m is a value of the parameter setting. ### Claim 3 (depends on 1) The device according to claim 1, wherein once the analogue digital converter of the reference channel has generated a sample at the same time as the channel placed in the ith position, where i is between 1 and N, the analogue digital converter of the reference channel will generate the next sample at the same time as the channel arranged in the (i+1 modulo N)th position. ### Claim 4 (depends on 1) The device according to claim 1, wherein the filter of each channel is a self-adaptive finite pulse response filter, said filter comprising 2·q+1 coefficients, q being an integer. ### Claim 5 (depends on 4) The device according to claim 4 wherein said coefficients of the filters of each channel are adapted using a Least Mean Squares Algorithm. ### Claim 6 (depends on 4) The device according to claim 4, wherein if i is an integer varying from 2 to q, the coefficients Ci are defined by a fixed relation to each other. ### Claim 7 (depends on 4) The device according to claim 4, wherein the central coefficient C0 and the first coefficient C1 of filter are updated by a self-adaptive method, the coefficient C−1, being equal to −C1 , the coefficients C−i, for i varying from 2 to q being equal to −Ci, the coefficients Ci, for i varying from 2 to q being determined from C1 by the relation C i = k ⁡ ( i ) · C 1 ( ( - 1 ) i + 1 · i ) with a factor k(i) dependent on i. ### Claim 8 (depends on 4) The device according to claims 4, wherein the factor k(i) is decreasing and varies from approximately 1 for i close to 2 towards zero for i tending towards q. ### Claim 9 (depends on 4) The device according to claim 4, wherein the central coefficient C0 and the first coefficient C1 of filter are updated by a self-adaptive method, the coefficient C−1 being equal to −C1, the coefficients C−i for i varying from 2 to q being equal to −Ci, the coefficients Ci for i varying from 2 to q being determined from C1 by the relation C i = C 1 i for even values of i and C i = C 1 - i and for odd values of i. ### Claim 10 (depends on 4) The device according to claim 4, wherein the filter of each channel operates at the required sampling frequency, by oversampling in a ratio N at the input to said filter. ### Claim 11 (depends on 10) The device according to claim 10, wherein the samples available at a given time on one of the other channels are used at the input to said filter, the samples input to the filter being input at the required sampling frequency. ### Claim 12 Analog digital conversion device receiving an analog signal at its input and outputting a digital signal at a required sampling frequency (Fe), said device comprising a number N of analog digital converters distributed in N channels, each analog digital converter having a sampling frequency N times lower than the required sampling frequency (Fe), said analog digital converters having clock signals controlling their sampling frequency, offset in time from each other by one period (Δ) of a signal at the required sampling frequency (Fe), the digital signal being built up from samples delivered to the output from each channel, said analog digital conversion device comprising a reference channel, said reference channel comprising an analog digital converter generating samples of the analog signal, each channel comprising an equalizer filter, said filter receiving a digital signal at its input output by the analog digital converter on the channel on which it is located and an error signal, said filter outputting a filtered digital signal s(n) corrected for errors deduced from the error signal, the error signal corresponding to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analog digital converter of the reference channel, the coefficients of said filter being adjusted to present the response that best minimizes the error signal, wherein the filter of each channel is a self-adaptive finite pulse response filter, said filter comprising 2·q+1 coefficients, q being an integer, and the central coefficient C0 and the first coefficient C1 of filter are updated by a self-adaptive method, the coefficient C−1 being equal to −C1, the coefficients C−i for i varying from 2 to q being equal to −Ci, the coefficients Ci , for i varying from 2 to q being determined from C1 by the relation C i = k ⁡ ( i ) · C 1 ( ( - 1 ) i + 1 · i ) with a factor k(i) dependent on i. ### Claim 13 Analog digital conversion device receiving an analog signal at its input and outputting a digital signal at a required sampling frequency (Fe), said device comprising a number N of analog digital converters distributed in N channels, each analog digital converter having a sampling frequency N times lower than the required sampling frequency (Fe), said analog digital converters having clock signals controlling their sampling frequency, offset in time from each other by one period (Δ) of a signal at the required sampling frequency (Fe), the digital signal being built up from samples delivered to the output from each channel, said Analog digital conversion device comprising a reference channel, said reference channel comprising an analog digital converter generating samples of the analog signal, each channel comprising an equalizer filter, said filter receiving a digital signal at its input output by the analog digital converter on the channel on which it is located and an error signal, said filter outputting a filtered digital signal s(n) corrected for errors deduced from the error signal, the error signal corresponding to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analog digital converter of the reference channel, the coefficients of said filter being adjusted to present the response that best minimizes the error signal, wherein the filter of each channel is a self-adaptive finite pulse response filter, said filter comprising 2·q+1 coefficients, q being an integer, and the filter of each channel operates at the required sampling frequency (Fe), by oversampling in a ratio N at the input to said filter. ### Claim 14 Analog digital conversion device receiving an analog signal at its input and outputting a digital signal at a required sampling frequency (Fe), said device comprising a number N of analog digital converters distributed in N channels, each analog digital converter having a sampling frequency N times lower than the required sampling frequency (Fe), said analog digital converters having clock signals controlling their sampling frequency, offset in time from each other by one period (Δ) of a signal at the required sampling frequency (Fe), the digital signal being built up from samples delivered to the output from each channel, said analog digital conversion device comprising a reference channel, said reference channel comprising an analog digital converter generating samples of the analog signal, each channel comprising an equalizer filter, and a summer connected to an output of said equalizer filter and connected to an output of the analog digital converter of the reference channel, said filter receiving a digital signal at its input output by the analog digital converter on the channel on which it is located and an error signal output by said summer, said filter outputting a filtered digital signal s(n) corrected for errors deduced from the error signal, the error signal corresponding to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analog digital converter of the reference channel, the coefficients of said filter being adjusted to present the response that best minimizes the error signal.