# US 7,466,188 B2 · Stress control mechanism for use in high-voltage applications in an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,188 B2 - Document ID: US7466188B2 - Status: Granted - Kind: B2 - Application number: 11/614,750 - Filed: 2006-12-21 - Published: 2008-06-26 - Granted: 2008-12-16 - Earliest claimed: 2006-12-21 - Assignees: International Business Machines Corporation - Inventors: John A. Fifield - Web page: https://patentgrep.com/patent/US7466188B2 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - H03K 17/063: {in field-effect transistor switches} - H03K 17/08142: {in field-effect transistor switches} - H03K 17/6872: {using complementary field-effect transistors} - H03K 2217/0027: Measuring means of, e.g. currents through or voltages across the switch - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level. ## Claims ### Claim 1 An integrated circuit designed to substantially operate at a supply voltage, comprising: circuitry requiring a boosted voltage relative to the supply voltage; a voltage pump that includes an output device in electrical communication with said circuitry so as to provide said circuitry with said boosted voltage, said output device driven by a gate voltage having a gate drive level and including a gate-oxide having an excessive stress voltage level; and a gate voltage controller for generating said gate drive level so as to maintain said gate oxide below said excessive stress level; wherein: said gate voltage has a down level and said gate voltage controller is operatively configured to maintain via an analog signal said gate oxide below said excessive stress level by adjusting said down level; said gate voltage controller is operatively configured to adjust said down level by generating an offset voltage; said gate voltage controller includes a first resistance and is configured to generate said offset voltage as a function of directing a predetermined first current through said first resistance; and said gate voltage controller is configured to generate said predetermined first current as a function of a difference between a first reference voltage and a second reference voltage. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein said second reference voltage is a fraction of the supply voltage. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein said gate voltage controller is configured to make said predetermined first voltage equal to zero volts when the supply voltage is at a predetermined level and greater than zero volts when the supply voltage is greater than said predetermined level. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein said gate voltage controller comprises a second resistance, a first unity gain amplifier coupled to a first voltage proportional to the supply voltage, and a second unity gain amplifier coupled to a second voltage that is fixed, said gate voltage controller operatively configured to generate said predetermined first current as a function of directing a second predetermined current through said second resistor via said first unity gain amplifier and said second unity gain amplifier. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein said gate voltage controller comprises an output inverter having a down level and said offset voltage is a function of said down level of said output inverter. ### Claim 6 An integrated circuit designed to operate at a supply voltage, comprising: voltage pump circuitry that includes an output device having a gate drive level and including a gate oxide having an excessive stress level; and a gate voltage controller electrically connected to said output device so as to provide said gate drive level, said gate voltage controller configured to vary said gate drive level as a function of said supply voltage; wherein said gate voltage controller is configured to generate said gate drive level as a function of a reference current. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein said gate voltage controller includes a current generator circuit for generating said reference current as a function of a first predetermined reference voltage and a second predetermined reference voltage. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein said current generator circuit comprises a first unity gain amplifier responsive to said first predetermined reference voltage and a second unity gain amplifier responsive to said second predetermined reference voltage. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein said second unity gain amplifier has an output node, said reference current occurring on said output node when said current generator circuit is operating. ### Claim 10 An integrated circuit, comprising: a voltage pump circuit including an output transistor having a gate input and responsive to a gate drive level; a voltage pump control circuit electrically connected to said gate input of said output transistor and configured to output said gate drive level in response to a reference current; a reference current generator electrically connected to said voltage pump control circuit so as to provide said voltage pump control circuit with said reference current; said reference current generator configured to generate said reference current as a function of a first reference voltage and a second reference voltage; a first reference voltage generator electrically connected to said reference current generator for providing said first reference voltage to said reference current generator; and a second reference voltage generator electrically connected to said reference current generator for providing said second reference voltage to said current generator. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein said voltage pump control circuit includes an inverter having an output directly connected to said gate input of said output transistor of said voltage pump circuit. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein said inverter has a low-voltage rail node and further includes a voltage offset transistor having an output in electrical communication with said low-voltage rail, said voltage offset transistor having a gate responsive to said reference current. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein said reference current generator includes a first unity gain amplifier electrically connected to said first reference voltage generator for receiving said first reference voltage and a second unity gain amplifier electrically connected to said second reference voltage generator for receiving said second reference voltage, said second unity gain amplifier having an output directly electrically connected to said gate of said voltage offset transistor. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein said first unity gain amplifier has a first input and said second unity gain amplifier has a second input, wherein said first input and said second input are electrically coupled to one another across a resistance.