# US 7,466,175 B2 · Capacitance multiplier circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,175 B2 - Document ID: US7466175B2 - Status: Granted - Kind: B2 - Application number: 11/617,826 - Filed: 2006-12-29 - Published: 2008-07-03 - Granted: 2008-12-16 - Earliest claimed: 2006-12-29 - Assignees: Motorola, Inc. - Inventors: Joe M. Smith; Gary P. English - Web page: https://patentgrep.com/patent/US7466175B2 ## CPC - H03H 11/483: {Simulating capacitance multipliers} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/347: in integrated circuits - H03F 2200/456: A scaled replica of a transistor being present in an amplifier - H03F 2200/546: A tunable capacitance being present in an amplifier circuit - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03F: AMPLIFIERS ## Abstract An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise. ## Claims ### Claim 1 An integrated circuit including a capacitance multiplier, comprising: a reference capacitor coupled between a first node and a second node, wherein the reference capacitor has a reference capacitor current; and a current mirror arrangement coupled between the second node and a point of reference potential, wherein the current mirror arrangement includes a first transistor Q1 having a first terminal coupled to the second node, a second transistor Q2 having a first terminal coupled to the first node and an operation amplifier coupled between the second node and a second terminal of the first transistor and the second transistor Q2 and the point of reference potential, wherein the current mirror arrangement has a current gain factor N, and wherein the current mirror arrangement varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. ### Claim 2 (depends on 1) The integrated circuit as recited in claim 1, wherein the current mirror arrangement includes: a first resistor R1 coupled between the second terminal of the first transistor Q1 and an output of the operation amplifier, and a second resistor R2 coupled between the second terminal of the second transistor Q2 and the output of the and the operation amplifier. ### Claim 3 (depends on 2) The integrated circuit as recited in claim 2, wherein the first resistor R1 and the second resistor R2 are configured in such a way that reduces the amount of noise introduced to the capacitance multiplier by the first transistor Q1 and the second transistor Q2. ### Claim 4 (depends on 1) The integrated circuit as recited in claim 1, wherein the current gain factor N is the ratio of the area of Q2 to the area of Q1. ### Claim 5 (depends on 1) The integrated circuit as recited in claim 1, further comprising a bias current source arrangement coupled to the reference capacitor and coupled to the current mirror arrangement. ### Claim 6 (depends on 1) The integrated circuit as recited in claim 1, wherein the current mirror arrangement is configured in such a way that reduces the amount of parasitic resistance within the capacitance multiplier. ### Claim 7 An integrated circuit including a phase-locked loop (PLL) loop filter circuit, comprising: a loop filter capacitor coupled between a first node and a first intermediate node; a loop filter resistor coupled between the first node and the first intermediate node; a capacitance multiplier coupled between the intermediate node and a point of reference potential, wherein the capacitance multiplier includes a reference capacitor coupled between the first intermediate node and a second intermediate node, wherein the reference capacitor has a reference capacitor current associated therewith, and a current mirror arrangement coupled between the second intermediate node and the point of reference potential, wherein the current mirror arrangement includes a first transistor Q1 having a first terminal coupled to the second intermediate node, a second transistor Q2 having a first terminal coupled to the first intermediate node, and an operation amplifier coupled between the second intermediate node and a second terminal of the first transistor and, the second transistor Q2 and the point of reference potential, wherein the current mirror arrangement is configured in such a way that reduces the amount of parasitics within the capacitance multiplier. ### Claim 8 (depends on 7) The integrated circuit as recited in claim 7, wherein the current mirror arrangement is configured in such a way that reduces the amount of noise introduced to the capacitance multiplier by at least a portion of the current mirror arrangement. ### Claim 9 (depends on 7) The integrated circuit as recited in claim 7, wherein the current mirror arrangement has a gain factor N, and wherein the current mirror arrangement varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. ### Claim 10 (depends on 7) The integrated circuit as recited in claim 7, wherein the current mirror arrangement includes: a first resistor R1 coupled between the second terminal of the first transistor Q1 and an output of the operation amplifier, and a second resistor R2 coupled between the second terminal of the second transistor Q2 and an output of the and the operation amplifier. ### Claim 11 (depends on 10) The integrated circuit as recited in claim 10, wherein the current gain factor N is the ratio of the area of Q2 to the area of Q1. ### Claim 12 (depends on 7) The integrated circuit as recited in claim 7, further comprising a bias current source arrangement coupled to the reference capacitor and coupled to the current mirror arrangement, wherein the bias current source arrangement determines the current through the current mirror arrangement, which varies the reference capacitor current. ### Claim 13 (depends on 7) The integrated circuit as recited in claim 7, wherein the first node is an input node, and wherein the integrated circuit further comprises a third loop filter resistor coupled between the input node and an output node, and a third loop filter capacitor coupled between the output node and the point of reference potential.