# US 7,466,159 B2 · Semiconductor integrated circuit having multiple semiconductor chips with signal terminals

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- Number: US 7,466,159 B2
- Document ID: US7466159B2
- Status: Granted
- Kind: B2
- Application number: 11/586,560
- Filed: 2006-10-26
- Published: 2007-05-17
- Granted: 2008-12-16
- Earliest claimed: 2005-11-16
- Assignees: Denso Corporation
- Inventors: Naoki Ito; Hideaki Ishihara; Yoshinori Teshima; Chikara Kobayashi
- Web page: https://patentgrep.com/patent/US7466159B2

## CPC

- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G01R 31/31926: {Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A semiconductor integrated circuit includes: a package; semiconductor chips in the package including a signal terminal; and a wiring connecting signal terminals. One semiconductor chip is a test object chip including a probe terminal and a test object terminal. The probe terminal connects to an external terminal for testing the test object terminal. The test object chip further includes: a common wiring for connecting the probe terminal and the test object terminal; a first switch for connecting/disconnecting the probe terminal and the common wiring; a second switch for connecting/disconnecting the test object terminal and the common wiring; and a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal.

## Claims

### Claim 1

A semiconductor integrated circuit comprising:
a package;
a plurality of semiconductor chips disposed in the package, wherein each semiconductor chip includes a signal terminal; and
a wiring for connecting signal terminals of two semiconductor chips of the semiconductor chips, wherein one of the two semiconductor chips is defined as a test object chip, the signal terminal of which is to be tested, wherein
the signal terminal of the test object chip includes a probe terminal and a test object terminal,
the probe terminal connects to an external terminal so that the test object terminal is tested through the external terminal, and
the test object chip further includes:
a common wiring for connecting the probe terminal and the test object terminal;
a first switch for connecting and disconnecting the probe terminal and the common wiring;
a second switch for connecting and disconnecting the test object terminal and the common wiring; and
a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal,
wherein the test object chip further includes a signal interrupting element for interrupting a signal, which is to be inputted into the test object terminal of the test object chip from other semiconductor chips.

### Claim 2 (depends on 1)

The circuit according to claim 1, wherein
the test object chip further includes an electric potential applying element for applying a predetermined electric potential to the common wiring.

### Claim 3

A semiconductor integrated circuit comprising:
a package;
a plurality of semiconductor chips disposed in the package, wherein each semiconductor chip includes a signal terminal; and
a wiring for connecting signal terminals of two semiconductor chips of the semiconductor chips, wherein one of the two semiconductor chips is defined as a test object chip, the signal terminal of which is to be tested, wherein
the signal terminal of the test object chip includes a probe terminal and a test object terminal,
the probe terminal connects to an external terminal so that the test object terminal is tested through the external terminal, and
the test object chip further includes:
a common wiring for connecting the probe terminal and the test object terminal;
a first switch for connecting and disconnecting the probe terminal and the common wiring;
a second switch for connecting and disconnecting the test object terminal and the common wiring;
a test signal interrupting element for interrupting the test signal to be inputted into an input circuit of the probe terminal;
an oscillation circuit for generating a clock signal and for supplying the clock signal to the test object chip;
an external clock terminal connecting to an external circuit so that an external clock signal is inputted into the test object chip from the external circuit; and
a selecting circuit for selecting one of the external clock terminal and the oscillation circuit so that the clock signal or the external clock signal is supplied to the test object chip, wherein
the selecting circuit selects the external clock terminal in an initial state of testing the test object terminal, and
the selecting circuit selects the oscillation circuit when the test object terminal is not tested.

### Claim 4 (depends on 3)

The circuit according to claim 3, wherein
the selecting circuit is capable of switching between the external clock terminal and the oscillation circuit when the test object terminal is tested.

### Claim 5 (depends on 3)

The circuit according to claim 3, wherein
the external clock terminal is connected to the signal terminals of other semiconductor chips.

### Claim 6 (depends on 3)

The circuit according to claim 3, wherein
the test object chip further includes an electric potential applying element for applying a predetermined electric potential to the common wiring.