# US 7,466,158 B2 · Multilayer semiconductor device

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- Number: US 7,466,158 B2
- Document ID: US7466158B2
- Status: Granted
- Kind: B2
- Application number: 11/254,703
- Filed: 2005-10-21
- Published: 2006-04-27
- Granted: 2008-12-16
- Earliest claimed: 2004-10-21
- Assignees: Elpida Memory, Inc.
- Inventors: Yukitoshi Hirose
- Web page: https://patentgrep.com/patent/US7466158B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.

## Claims

### Claim 1

A multilayer semiconductor device comprising:
a plurality of layered semiconductor chips, wherein a first semiconductor chip of the layered semiconductor chips comprises a signal line not connected to an external circuit terminal of the multilayer semiconductor device;
a switching transistor or selector disposed in a second semiconductor chip different from the first semiconductor chip of the layered semiconductor chips; and
a test pad for connecting to a test stub line is disposed in the second semiconductor chip,
wherein the switching transistor or selector connects the signal line to the test stub line when each semiconductor chip is tested and separates the signal line from the test stub line during the normal operation.

### Claim 2 (depends on 1)

The multilayer semiconductor device according to claim 1 , wherein the selector selects one signal line from N signal lines in the plurality of layered semiconductor chips and connects the selected signal line to the test stub line.

### Claim 3 (depends on 1)

The multilayer semiconductor device according to claim 1, wherein the plurality of layered semiconductor chips comprise a through-electrode.

### Claim 4 (depends on 1)

The multilayer semiconductor device according to claim 1, wherein the plurality of layered semiconductor chips are System-On-Chips having a plurality of functions.

### Claim 5 (depends on 1)

The multilayer semiconductor device according to “claim 1, wherein the plurality of layered semiconductor chips comprises a plurality of layered semiconductor devices.”

### Claim 6

A multilayer semiconductor device comprising:
a plurality of layered semiconductor chips, wherein a first semiconductor chip of the layered semiconductor chips comprises a signal line not connected to an external circuit terminal of the multilayer semiconductor device, and
a separating element disposed in a second semiconductor chip different from the first semiconductor chip of the layered semiconductor chips, which connects the signal line to a test stub line when each semiconductor chip is tested and separates the signal line from the test stub line during the normal operation.