# US 7,466,157 B2 · Contactless interfacing of test signals with a device under test > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,466,157 B2 - Document ID: US7466157B2 - Status: Granted - Kind: B2 - Application number: 10/772,970 - Filed: 2004-02-05 - Published: 2005-08-11 - Granted: 2008-12-16 - Earliest claimed: 2004-02-05 - Assignees: FormFactor, Inc. - Inventors: Charles A. Miller - Web page: https://patentgrep.com/patent/US7466157B2 ## CPC - G01R 1/0491: {for testing integrated circuits on wafers, e.g. wafer-level test cartridge} - G01R 31/3025: {Wireless interface with the DUT} - G01R 1/07: Non contact-making probes - G01R 1/07378: {using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device. ## Claims ### Claim 1 A semiconductor wafer comprising: a plurality of dies each comprising functional circuitry; electrically conductive structures configured to contactlessly receive test signals from a test board in physical proximity to said wafer for testing said functional circuitry of said dies; and an electrically conductive shielding plane disposed between at least part of ones of said conductive structures and at least part of said functional circuitry of said dies, said shielding plane shielding said dies from electrical interference. ### Claim 2 (depends on 1) The semiconductor wafer of claim 1, wherein each die comprises a set of said conductive structures. ### Claim 3 (depends on 2) The semiconductor wafer of claim 2, wherein each of said conductive structures in a set of said conductive structures are electrically connected to a plurality of said dies. ### Claim 4 (depends on 1) The semiconductor wafer of claim 1 further comprising a transmitter configured to transmit test signals on at least one of said conductive structures. ### Claim 5 (depends on 4) The semiconductor wafer of claim 4, wherein each of said dies comprises such a transmitter. ### Claim 6 (depends on 1) The semiconductor wafer of claim 1 further comprising a receiver configured to receive a test signal induced on at least one of said conductive structures. ### Claim 7 (depends on 6) The semiconductor wafer of claim 6, wherein each of said dies comprises such a receiver. ### Claim 8 (depends on 1) The semiconductor wafer of claim 1 further comprising a transceiver configured to transmit test signals on at least one of said conductive structures and to receive a test signal induced on at least one of said conductive structures. ### Claim 9 (depends on 8) The semiconductor wafer of claim 8, wherein each of said dies comprises such a transceiver. ### Claim 10 (depends on 1) The semiconductor wafer of claim 1 further comprising built in self test circuitry. ### Claim 11 The semiconductor wafer of 1, wherein said electrically conductive shielding plane is sized to substantially cover said dies. ### Claim 12 (depends on 11) The semiconductor wafer of claim 11, wherein said shielding plane is a solid plate structure. ### Claim 13 The semiconductor wafer of 1, wherein said shielding plane comprises openings through which said conductive structures are electrically connected to said functional circuitry of said dies. ### Claim 14 A semiconductor wafer comprising: a plurality of dies each comprising functional circuitry; means for receiving test signals from ones of a plurality of tester channels on a test board in physical proximity to said wafer without physically contacting said tester channels; and an electrically conductive shielding plane disposed between at least part of said means for receiving test signals and at least part of said functional circuitry of said dies, said shielding plane shielding said dies from electrical interference. ### Claim 15 (depends on 14) The semiconductor wafer of claim 14 further comprising means for sending test signals to ones of said tester channels without physically contacting said tester channels. ### Claim 16 (depends on 14) The semiconductor wafer of claim 14 further comprising means for controlling communications with said tester channels. ### Claim 17 (depends on 14) The semiconductor wafer of claim 14, wherein: each die further comprises communications control circuitry; and said means for receiving test signals is electrically connected to said communications control circuitry through openings in said plane. ### Claim 18 (depends on 17) The semiconductor wafer of claim 17, wherein said means for receiving test signals is electrically connected to said plane. ### Claim 19 (depends on 18) The semiconductor wafer of claim 18, wherein said plane is a ground plane. ### Claim 20 (depends on 17) The semiconductor wafer of claim 17, wherein said communications control circuitry is configured to control communication of said test signals through said conductive structures to said tester channels on said test board, said communication control circuitry further configured to control communication of said test signals into and output of said functional circuitry of said die. ### Claim 21 (depends on 1) The semiconductor wafer of claim 1 further comprising: a plurality of electrically conductive planes disposed between said conductive structures and said functional circuitry; and insulating material disposed between said planes. ### Claim 22 (depends on 21) The semiconductor wafer of claim 21, wherein one of said planes is configured as a power distribution plane, and another of said planes is configured as a ground plane, wherein one of said power distribution plane or said ground plane comprises said shielding plane. ### Claim 23 (depends on 1) The semiconductor wafer of claim 1, wherein: each die further comprises communications control circuitry; and ones of said conductive structures are electrically connected to said communications control circuitry through openings in said plane. ### Claim 24 (depends on 23) The semiconductor wafer of claim 23, wherein at least one of said conductive structures is electrically connected at one end to said communications control circuitry and is electrically connected at another end to said plane. ### Claim 25 (depends on 24) The semiconductor wafer of claim 24, wherein said plane is a ground plane. ### Claim 26 (depends on 23) The semiconductor wafer of claim 23, wherein said communications control circuitry is configured to control communication of said test signals through said conductive structures to said test board, said communication control circuitry further configured to control communication of said test signals into and output of said functional circuitry of said die. ### Claim 27 (depends on 14) The semiconductor wafer of claim 14 further comprising: a plurality of electrically conductive planes disposed between said conductive structures and said functional circuitry; and insulating material disposed between said planes. ### Claim 28 (depends on 27) The semiconductor wafer of claim 27, wherein one of said planes is configured as a power distribution plane, and another of said planes is configured as a ground plane, wherein one of said power distribution plane or said ground plane comprises said shielding plane. ### Claim 29 The semiconductor wafer of 14, wherein said electrically conductive shielding plane is sized to substantially cover said dies. ### Claim 30 (depends on 29) The semiconductor wafer of claim 29, wherein said shielding plane is a solid plate structure. ### Claim 31 The semiconductor wafer of 14, wherein said shielding plane comprises openings through which said means for receiving test signals is electrically connected to said functional circuitry of said at least one of said dies.