# US 7,465,996 B2 · Semiconductor device and method for fabricating the same

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- Number: US 7,465,996 B2
- Document ID: US7465996B2
- Status: Granted
- Kind: B2
- Application number: 11/491,930
- Filed: 2006-07-25
- Published: 2007-03-15
- Granted: 2008-12-16
- Earliest claimed: 2005-09-15
- Assignees: Panasonic Corporation
- Inventors: Yoshihiro Satou; Chiaki Kudou
- Web page: https://patentgrep.com/patent/US7465996B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0174: {the gate conductors being silicided}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided first gate electrode; and a second MIS transistor formed in the second region of the semiconductor substrate and including a stack of a second gate insulating film and a fully-silicided second gate electrode. The second gate electrode has a gate length larger than that of the first gate electrode. A middle portion in the gate length direction of the second gate electrode has a thickness smaller than the thickness of the first gate electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate divided into a first region and a second region;
a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided first gate electrode; and
a second MIS transistor formed in the second region of the semiconductor substrate and including a stack of a second gate insulating film and a fully-silicided second gate electrode,
wherein the second gate electrode has a gate length larger than that of the first gate electrode,
a middle portion in a gate length direction of the second gate electrode has a thickness smaller than the thickness of the first gate electrode,
first sidewalls made of an insulating film are formed on both sides of the first gate electrode,
second sidewalls made of an insulating film are formed on both sides of the second gate electrode, and
a height of an upper surface of the middle portion in the gate length direction of the second gate electrode is lower than heights of upper ends of the second sidewalls, and
heights of the second sidewalls measured from the surface of the second region are substantially identical with heights of the first sidewalls measured from the surface of the first region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second gate electrode has a flat upper surface.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second gate electrode has a recess in cross section in the gate length direction.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first MIS transistor has a first impurity layer formed in the first region below both sides of the first gate electrode, and the second MIS transistor includes a second impurity layer formed in the second region below both sides of the second gate electrode.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first MIS transistor and the second MIS transistor are MIS transistors of an identical conductivity type.

### Claim 6

A method for fabricating a semiconductor device, the method comprising the steps of:
(a) forming a gate insulating film, a silicon film and a protective film in this order over a semiconductor substrate divided into a first region and a second region;
(b) patterning at least the protective film and the silicon film, thereby forming a first gate-electrode formation film including a first protective film and a first gate silicon film formed out of the protective film and the silicon film, respectively, in the first region, and also forming a second gate-electrode formation film including a second protective film and a second gate silicon film formed out of the protective film and the silicon film, respectively, in the second region, the second gate-electrode formation film having a gate length larger than that of the first gate-electrode formation film;
(c) forming sidewalls of an insulating film on side faces of the first gate-electrode formation film and the second gate-electrode formation film;
(d) forming an impurity layer in the first region and the second region of the semiconductor substrate using, as masks, the first gate-electrode formation film and the second gate-electrode formation film provided with the sidewalls;
(e) removing the first protective film and the second protective film after the step (d), thereby exposing the first gate silicon film and the second gate silicon film;
(f) reducing the thickness of at least a middle portion in a gate length direction of the second gate silicon film so that the thickness is smaller than the thickness of the first gate silicon film, after the step (e); and
(g) forming a metal film on the first gate silicon film and the second gate silicon film and then performing heat treatment on the metal film after the step (f), thereby fully siliciding the first gate silicon film and the second gate silicon film.

### Claim 7 (depends on 6)

The method of claim 6, wherein in the step (f), etching is performed on the entire second gate silicon film so that the entire second gate silicon film has a thickness smaller than that of the first gate silicon film.

### Claim 8 (depends on 6)

The method of claim 6, wherein in the step (f), only the middle portion in the gate length direction of the second gate silicon film is selectively etched so that the middle portion of the second gate silicon film has a thickness smaller than that of the first gate silicon film.

### Claim 9 (depends on 6)

The method of claim 6, further comprising the step of forming an interlayer insulating film over the first region and the second region to cover the first protective film and the second protective film therewith and then planarizing an upper surface of the interlayer insulating film to expose upper surfaces of the first protective film and the second protective film, between the step of forming the impurity layer and the step of removing the first protective film,
wherein an etch rate of the interlayer insulating film is lower than that of each of the first protective film and the second protective film.

### Claim 10 (depends on 6)

The method of claim 6, further comprising the step of forming an extension impurity layer in the first region and the second region of the semiconductor substrate using the first gate-electrode formation film and the second gate-electrode formation film as masks, between the step of patterning the first gate-electrode formation film and the second gate-electrode formation film and the step of forming the sidewalls.

### Claim 11 (depends on 6)

The method of claim 6, further comprising the step of siliciding an upper portion of the impurity layer, between the step of forming the impurity layer and the step of removing the first protective film.