# US 7,465,882 B2 · Ceramic substrate grid structure for the creation of virtual coax arrangement

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,465,882 B2
- Document ID: US7465882B2
- Status: Granted
- Kind: B2
- Application number: 11/610,082
- Filed: 2006-12-13
- Published: 2008-06-19
- Granted: 2008-12-16
- Earliest claimed: 2006-12-13
- Assignees: International Business Machines Corporation
- Inventors: Wiren D. Becker; Zhaoqing Chen; George Katopis
- Web page: https://patentgrep.com/patent/US7465882B2

## CPC

- H05K 1/0224: {Patterned shielding planes, ground planes or power planes (H05K1/0253 takes precedence)}
- H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors}
- H10W 42/267: {Patterned shielding planes}
- H10W 70/635: {Through-vias}
- H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)}
- H05K 2201/09609: Via grid, i.e. two-dimensional array of vias or holes in a single plane
- H05K 2201/09618: Via fence, i.e. one-dimensional array of vias
- H05K 2201/09681: Mesh conductors, e.g. as a ground plane
- H10W 44/212: {Coaxial feed-throughs in substrates}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- Y10T 29/49126: Assembling bases
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49155: Manufacturing circuit on or in base
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

## Claims

### Claim 1

A conductive shielding structure for an electrical signal conductor in a vertical via in a substrate for interconnecting integrated circuit chips, said shielding structure comprising:
at least three vertically oriented vias with conductive material therein connecting power plane grids disposed on opposite sides of said signal conductors; and
at least three vertically oriented vias with conductive material therein connecting ground plane grids disposed on opposite sides of said signal conductors;
said vias being disposed in an alternating pattern surrounding said signal conductor.

### Claim 2 (depends on 1)

The structure of claim 1 further including a conductive pattern extending between said vias in at least one of said power planes, said conductive pattern surrounding said signal conductor.

### Claim 3 (depends on 1)

The structure of claim 1 further including a conductive pattern extending between said vias in at least one of said ground planes, said conductive pattern surrounding said signal conductor.

### Claim 4 (depends on 2)

The structure of claim 2 further including a conductive pattern surrounding said signal conductor in all power planes through which said signal conductor passes.

### Claim 5 (depends on 3)

The structure of claim 3 further including a conductive pattern surrounding said signal conductor in all ground planes through which said signal conductor passes.