# US 7,465,664 B2 · Method for fabricating semiconductor device to lower source/drain sheet resistance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,465,664 B2 - Document ID: US7465664B2 - Status: Granted - Kind: B2 - Application number: 11/408,940 - Filed: 2006-04-24 - Published: 2007-07-05 - Granted: 2008-12-16 - Earliest claimed: 2005-12-30 - Assignees: Industrial Technology Research Institute - Inventors: Ching-Yuan Ho; Chen-Hsin Lien - Web page: https://patentgrep.com/patent/US7465664B2 ## CPC - H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon} - H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions} - H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures} - H10W 20/033: {in openings in dielectrics} - H10W 20/047: {by introducing additional elements therein} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered. ## Claims ### Claim 1 A method for fabricating a semiconductor device to lower source/drain sheet resistance, comprising: providing a semiconductor device with at least one gate region and two junction regions; forming a dielectric layer on the semiconductor device, wherein the dielectric layer is provided with a plurality of contact windows corresponding to the gate region and the two junction regions to expose a part of the gate region and the junction regions; depositing a silicon layer or SiGe epitaxial layer in the plurality of contact windows to cover the exposed gate region and the exposed junction regions; depositing a metal layer to cover the silicon layer or the SiGe epitaxial layer in the contact windows and the rest of the dielectric layer; and conducting a heat treatment of the semiconductor device in a nitrogen-containing environment, such that the silicon layer or the SiGe epitaxial layer and the metal layer are reacted, so as to convert the silicon layer or the SiGe epitaxial layer into a silicide. ### Claim 2 (depends on 1) The fabricating method according to claim 1, further comprising a step of forming a barrier layer on the metal layer. ### Claim 3 (depends on 2) The fabricating method according to claim 2, wherein the barrier layer is formed by nitridation. ### Claim 4 (depends on 2) The fabricating method according to claim 2, wherein the barrier layer is formed by reactive sputtering. ### Claim 5 (depends on 2) The fabricating method according to claim 2, further comprising a step of forming a plurality of metal plugs in the contact windows. ### Claim 6 (depends on 1) The fabricating method according to claim 1, wherein the silicon layer or the SiGe epitaxial layer is formed by selective epitaxial growth (SEG). ### Claim 7 (depends on 1) The fabricating method according to claim 1, wherein the metal layer is selected from the group consisting of Ti, Co, and Ni. ### Claim 8 (depends on 1) The fabricating method according to claim 1, wherein the step of conducting a heat treatment is achieved by a rapid thermal annealing process (RTP). ### Claim 9 A method for fabricating a semiconductor device to lower source/drain sheet resistance, comprising: providing a semiconductor device with at least one gate region and two junction regions; depositing a silicon layer or SiGe epitaxial layer on the gate region and the two junction regions; forming a dielectric layer on the semiconductor device, wherein the dielectric layer is provided with a plurality of contact windows corresponding to the gate region and the two junction regions, so as to expose a part of the silicon layer or SiGe epitaxial layer ob the gate region and the two junction regions; depositing a metal layer to cover the exposed silicon layer or the exposed SiGe epitaxial layer in the contact windows and the rest of the dielectric layer; and conducting a heat treatment of the semiconductor device in a nitrogen-containing environment, such that the silicon layer or the SiGe epitaxial layer and the metal layer are reacted, so as to convert the silicon layer or the SiGe epitaxial layer into a silicide. ### Claim 10 (depends on 9) The fabricating method according to claim 9, further comprising a step of forming a barrier layer on the metal layer. ### Claim 11 (depends on 10) The fabricating method according to claim 10, wherein the barrier layer is formed by nitridation. ### Claim 12 (depends on 10) The fabricating method according to claim 10, wherein the barrier layer is formed by reactive sputtering. ### Claim 13 (depends on 10) The fabricating method according to claim 10, further comprising forming a plurality of metal plugs in the contact windows. ### Claim 14 (depends on 9) The fabricating method according to claim 9, wherein the silicon layer or the SiGe epitaxial layer is formed by SEG. ### Claim 15 (depends on 9) The fabricating method according to claim 9, wherein the metal layer is selected from the group consisting of Ti, Co, and Ni. ### Claim 16 (depends on 9) The fabricating method according to claim 9, wherein the step of conducting heat treatment is achieved by RTP.