# US 7,465,633 B2 · Methods of forming field effect transistors and capacitor-free dynamic random access memory cells

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- Number: US 7,465,633 B2
- Document ID: US7465633B2
- Status: Granted
- Kind: B2
- Application number: 11/622,584
- Filed: 2007-01-12
- Published: 2007-07-19
- Granted: 2008-12-16
- Earliest claimed: 2006-01-16
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Ki-whan Song; Chang-kyun Kim
- Web page: https://patentgrep.com/patent/US7465633B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 30/711: {having floating bodies}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.

## Claims

### Claim 1

A method of forming a field effect transistor, comprising:
forming a first semiconductor wafer having a channel region protrusion extending therefrom that is surrounded by an electrical isolation region, said channel region protrusion having a first width;
removing a portion of a backside of the first semiconductor wafer to define a semiconductor layer having a second width greater than the first width, said semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region;
forming a gate electrode extending opposite the channel region protrusion, on the primary surface; and
forming source and drain regions of a first conductivity type in the semiconductor layer, on opposite sides of the gate electrode, said source and drain regions defining a channel region therebetween that forms a non-rectifying junction with the channel region protrusion, which has a greater volume than the channel region.

### Claim 2 (depends on 1)

The method of claim 1, wherein said forming a first semiconductor wafer comprises:
selectively etching a front side of the first semiconductor wafer to define the channel region protrusion having exposed sidewalls that are separated from each other by the first width;
depositing an electrically insulating layer on the exposed sidewalls of the channel region protrusion; and
removing a portion of the electrically insulating layer to thereby define the electrical isolation region.

### Claim 3 (depends on 2)

The method of claim 2, wherein said removing a portion of the electrically insulating layer comprises planarizing the electrically insulating layer to define a planarized surface of the electrical isolation region.

### Claim 4 (depends on 3)

The method of claim 3, wherein said removing a portion of the backside of the first semiconductor wafer is preceded by bonding a second semiconductor wafer on the planarized surface.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second semiconductor wafer is electrically insulated from the channel region protrusion.

### Claim 6 (depends on 4)

The method of claim 4, wherein said forming source and drain regions comprises implanting source and drain region dopants into the semiconductor layer, using the gate electrode as an implant mask.

### Claim 7 (depends on 2)

The method of claim 2, wherein said removing a portion of the backside of the first semiconductor wafer comprises delaminating the portion of the backside of the first semiconductor wafer to thereby expose the semiconductor layer.

### Claim 8 (depends on 4)

The method of claim 4, wherein said removing a portion of the backside of the first semiconductor wafer comprises delaminating the portion of the backside of the first semiconductor wafer to thereby expose the semiconductor layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein said selectively etching a front side of the first semiconductor wafer is preceded by implanting hydrogen ions into the front side of the first semiconductor wafer to define a hydrogen-enhanced semiconductor layer buried within the first semiconductor wafer; and wherein said delaminating comprises delaminating the portion of the backside of the first semiconductor wafer along the hydrogen-enhanced semiconductor layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein said selectively etching a front side of the first semiconductor wafer is preceded by implanting electrically inert atoms from Group 0 of the periodic table into the front side of the first semiconductor wafer to define a buried layer having a concentration of inert atoms therein; and wherein said delaminating comprises delaminating the portion of the backside of the first semiconductor wafer along the buried layer.

### Claim 11

A method of forming a capacitor-free dynamic random access memory cell, comprising:
implanting hydrogen and/or inert atoms from Group 0 of the periodic table into a front side of a first semiconductor wafer to define a buried implant layer therein;
forming a first electrically insulating layer pattern on the front side of the semiconductor wafer;
selectively etching the front side of the semiconductor wafer to define a channel region protrusion having a first width extending therefrom, using the first electrically insulating pattern as an etching mask;
depositing a second electrically insulating layer on sidewalls of the channel region protrusion;
planarizing the second electrically insulating layer to thereby define an electrical isolation region surrounding the channel region protrusion;
bonding a second semiconductor wafer on a planarized surface of the electrical isolation region;
delaminating a portion of a backside of the first semiconductor wafer to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region, said first semiconductor wafer defined to have a second width greater than the first width;
forming a gate electrode extending opposite the channel region protrusion, on the primary surface; and
forming source and drain regions of first conductivity type in the semiconductor layer, on opposite sides of the gate electrode, said source and drain regions defining a channel region therebetween that forms a non-rectifying junction with the channel region protrusion, which has a greater volume than the channel region and operates as a charge storage region within the capacitor-free dynamic random access memory cell.

### Claim 12 (depends on 11)

The method of claim 11, wherein said delaminating comprises delaminating the portion of the backside of the first semiconductor wafer along the buried implant layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein said depositing a second electrically insulating layer comprises depositing the second electrically insulating layer on the first electrically insulating pattern; and wherein said planarizing comprises planarizing the second electrically insulating layer using the first electrically insulating pattern as a planarization stop layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein said bonding comprises bonding the second semiconductor wafer on the first electrically insulating pattern.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first electrically insulating pattern comprises a composite of nitride and oxide regions.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
depositing an inter-layer isolation layer on the source and drain regions; and
forming a contact hole that extends through the inter-layer isolation layer and the electrical isolation region and exposes a portion of the second semiconductor wafer.