# US 7,465,632 B2 · Method for forming buried doped region

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- Number: US 7,465,632 B2
- Document ID: US7465632B2
- Status: Granted
- Kind: B2
- Application number: 11/163,728
- Filed: 2005-10-28
- Published: 2006-09-28
- Granted: 2008-12-16
- Earliest claimed: 2005-03-25
- Assignees: Powerchip Semiconductor Corp.
- Inventors: Chiu-Tsung Huang; Su-Yuan Chang
- Web page: https://patentgrep.com/patent/US7465632B2

## CPC

- H10P 30/21: {of electrically active species}
- H10P 30/204: {into Group IV semiconductors}
- H10W 15/00: Highly-doped buried regions of integrated devices
- H10W 15/01: {Manufacture or treatment}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by the opening. Thereafter, a second insulating layer is formed on the substrate to fill the opening. The second insulating layer together with the first insulation layer form a third insulating layer. The third insulating layer is patterned to form an isolation layer that exposes the substrate and the buried doped region. The isolation layer extends in a second direction and crosses over the first direction. A semiconductor layer is formed on the substrate to fill the areas on the respective sides of the isolation layer.

## Claims

### Claim 1

A method for forming a buried doped region, comprising:
providing a substrate;
forming a first insulating layer on the substrate;
patterning the first insulating layer to form an opening that exposes a portion of the substrate, wherein the opening extends in a first direction;
forming a buried doped region in the substrate exposed by the opening;
forming a second insulating layer over the substrate to fill the opening, wherein the second insulating layer and the first insulating layer together form a third insulating layer;
patterning the third insulating layer to form an isolation layer that exposes a portion of the substrate and the buried doped region, wherein the isolation layer extends in a second direction such that the second direction and the first direction cross over each other; and
forming a semiconductor layer over the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the semiconductor layer comprises performing a chemical vapor deposition process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the material constituting the semiconductor layer is selected from a group consisting of mono crystalline silicon, polysilicon and amorphous silicon.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of forming the semiconductor layer comprises performing an epitaxial process.

### Claim 5 (depends on 4)

The method of claim 4, wherein the step of forming the semiconductor layer comprises using silane as the reactive gas.

### Claim 6 (depends on 1)

The method of claim 1, wherein the step of forming the first insulating layer and the second insulating layer comprises performing a chemical vapor deposition process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the material constituting the first insulating layer and the second insulating layer comprises silicon oxide.

### Claim 8 (depends on 7)

The method of claim 7, wherein the step of forming the first insulating layer and the second insulating layer comprises using tetra-ethyl-ortho-silicate (TEOS) as the reactive gas.

### Claim 9 (depends on 1)

The method of claim 1, wherein after forming the second insulating layer on the substrate, further comprises planarizing the second insulating layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the step of planarizing the second insulating layer comprises performing a chemical-mechanical polishing process or an etching back process.

### Claim 11 (depends on 1)

The method of claim 1, wherein the step of forming the buried doped region comprises performing an ion implant process.

### Claim 12 (depends on 1)

The method of claim 1, wherein the semiconductor layer exposes at least the isolation layer.

### Claim 13

A method for forming a buried doped region, comprising:
providing a substrate;
forming a first silicon oxide layer on the substrate;
patterning the first silicon oxide layer to form an opening that exposes a portion of the substrate, wherein the opening extends in a first direction;
forming a buried doped region in the substrate exposed by the opening;
forming a second silicon oxide layer over the substrate to fill the opening;
planarizing the second silicon oxide layer so that the second silicon oxide layer and the first silicon oxide layer together form a third silicon oxide layer;
patterning the third silicon oxide layer to form an isolation layer that exposes a portion of the substrate and the buried doped region, wherein the isolation layer extends in a second direction and the second direction and the first direction cross over each other; and
forming a semiconductor layer over the substrate, wherein the semiconductor layer exposes at least the isolation layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the step of forming the semiconductor layer comprises performing a chemical vapor deposition process.

### Claim 15 (depends on 14)

The method of claim 14, wherein the material constituting the semiconductor layer is selected from a group consisting of mono crystalline silicon, polysilicon and amorphous silicon.

### Claim 16 (depends on 13)

The method of claim 13, wherein the step of forming the semiconductor layer comprises performing an epitaxial process.

### Claim 17 (depends on 13)

The method of claim 13, wherein the step of forming the first silicon oxide layer and the second silicon oxide layer comprises performing a chemical vapor deposition process.

### Claim 18 (depends on 13)

The method of claim 13, wherein the step of forming the first silicon oxide layer and the second silicon oxide layer comprises using silane or tetra-ethyl-ortho-silicate (TEOS) as the reactive gas.

### Claim 19 (depends on 13)

The method of claim 13, wherein the step of planarizing the second silicon oxide layer comprises removing a portion of the first silicon oxide layer.

### Claim 20 (depends on 13)

The method of claim 13, wherein the step of planarizing the second silicon oxide layer comprises performing a chemical-mechanical polishing process or an etching back process.

### Claim 21 (depends on 13)

The method of claim 13, wherein the step of forming the buried doped region comprises performing an ion implant process.