Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology

A memory module comprising:

• a connector interface;
• a first signal path coupled to the connector interface;
• a first integrated circuit memory die;
• a second integrated circuit memory die;
• a first integrated circuit buffer die coupled to the first signal path, the first integrated circuit buffer die to receive first control information from the first signal path, wherein the first control information specifies an access to the first integrated circuit memory die;
• a second integrated circuit buffer die coupled to the first signal path, the second integrated circuit buffer die to receive second control information from the first signal path, wherein the second control information specifies an access to the second integrated circuit memory die;
• and
• a signal line to provide a first clock signal to the first integrated circuit buffer die and the second integrated circuit buffer die, wherein:
• the first integrated circuit buffer die generates a second clock signal using the first clock signal and provides the second clock signal to the first integrated circuit memory die;
• and
• the second integrated circuit buffer die generates a third clock signal using the first clock signal and provides the third clock signal to the first integrated circuit memory die.