US 7,463,626 B2 · Phase and frequency drift and jitter compensation in a distributed telecommunications switch

Abstract

Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Claims7

Dependent claims

A method for arbitrating bandwidth in a communications switch, comprising:

generating a repeating data frame having a plurality of rows;
making requests during row N for space in row N+1, where N is an integer;
buffering a predetermined number of requests;
and
granting one or more of the buffered requests based on priority.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/155,517Filed 24 May 2002 · continuation in part

Priority

21 Nov 2000

Published

US 2003/0091035 A115 May 2003

Granted

9 Dec 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H04L 12/6402
Hybrid switching systems: hybrid switching fabrics
H04J 3/0685
Clock or time synchronisation in a network: clock or time synchronisation in a node; Intranode synchronisation
H04J 3/0682
Clock or time synchronisation in a network: by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
H04J 3/0688
Clock or time synchronisation in a node; Intranode synchronisation: change of the master or reference, e.g. take-over or failure of the master

Phase and frequency drift and jitter compensation in a distributed telecommunications switch

Life of this patent

Phase and frequency drift and jitter compensation in a distributed telecommunications switch

Life of this patent

Abstract

Claims7