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US 7,463,514 B1Granted
Multi-level cell serial-parallel sense scheme for non-volatile flash memory
AssigneeIntel Corporation
InventorRezaul Haque
Life of this patent
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Abstract
A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.
Claims15
A method of sensing data in a multi-level cell memory, the method comprising:
- ramping a wordline of a memory cell to a first cell level;
- performing a first sense operation at a first reference current;
- determining a value of most significant bit data of the memory cell from the first sense operation;
- ramping the wordline to a second cell level;
- and
- performing a second sense operation,
- wherein if the most significant bit data is determined to equal 1, said performing a second sense operation occurs at a second reference current, wherein the second reference current is greater than the first reference current, and the method further comprises adjusting column load.
4 more elements
A sensing circuit for a multi-level cell memory, comprising:
- a flash cell coupled to a wordline;
- a sense amplifier to receive input from at least one sense line and output a signal to a bus;
- a cascode device capable of holding voltage steady for said at least one sense line and providing input to the sense amplifier;
- a decoding device coupled to the flash cell and the cascode device, and capable of receiving bitline selection signals;
- and
- wherein the sense amplifier includes a column load adjuster for varying the column load of the sensing circuit.
3 more elements
Dependencies are inferred from the claim text.