US 7,463,502 B2Granted

Ultra low-cost solid-state memory

AssigneeHitachi Global Storage Technologies Netherlands B.V.

InventorBarry Cushing Stipe

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Abstract

A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or hysteretic-resistor memory cells. Each tree structure corresponds to a bit line, has a trunk portion and at least one branch portion. The trunk portion of each tree structure extends from a corresponding bit line, and each tree structure corresponds to a plurality of layers. Each branch portion corresponds to at least one layer and extends from the trunk portion of a tree structure. Plate lines correspond to at least one layer and overlap the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions.

Claims25

Dependent claims

A method for reading and erasing a memory device, the memory device including a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction, a plurality of layers, each layer having an array of ferroelectric capacitor memory cells, each layer being substantially parallel to the first plane, a plurality of tree structures arranged into a plurality of rows, at least one tree structure corresponding to each bit line and having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the corresponding bit line, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers, and a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a ferroelectric capacitor memory cell being located at each intersection region in a layer,

the method comprising:
allowing each tree structure in at least one row to electrically float near a first predetermined voltage;
applying a second predetermined voltage V to a selected plate line;
detecting a potential of each tree structure in the at least one row;
determining whether each detected potential corresponds to a 0 or a 1 for each memory cell at the intersections of the selected plate line and the tree structures in the at least one row;
applying the first predetermined voltage to every tree structure in the at least one row;
and
applying the first predetermined voltage to the selected plate line.

5 more elements

A method for writing data to a previously erased memory device, the memory device including a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction, a plurality of layers, each layer having an array of ferroelectric capacitor memory cells, each layer being substantially parallel to the first plane, a plurality of tree structures arranged into a plurality of rows, at least one tree structure corresponding to each bit line and having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the corresponding bit line, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers, and a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a ferroelectric capacitor memory cell being located at each intersection region in a layer,

the method comprising:
applying a voltage V/3 to each tree structure in at least one row of tree structures;
applying a voltage 2V/3 to each plate line in the at least one row of tree structures;
applying a voltage V to a predetermined number of selected tree structures in the at least one row of tree structures;
applying a voltage 0 to a selected plate line where a data “1” will be written in a predetermined number of selected memory cells at the intersection of the first predetermined number of tree structures and the selected plate line;
applying a voltage 2V/3 to the selected plate line;
applying a voltage V/3 to the predetermined number of selected tree structures in the at least one row of tree structures;
applying a voltage 0 to each plate line in the at least one row of tree structures;
and
applying a voltage 0 to each tree structure in the at least one row of tree structures.

7 more elements

A method for reading and erasing a memory device, the memory device including a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction, a three-dimensional memory having a plurality of layers and a plurality of tree structures, each layer having a plurality of memory cells and the tree structures being arranged in a plurality of rows, each tree structure having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, and each branch portion of a tree structure extending from the trunk portion of the tree structure, a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one each layer of the three-dimensional memory, each respective plate line group overlapping the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions, a memory cell being located at each intersection region in a layer, and a plurality of plate-line driver transistors formed on the substrate and arranged in a two-dimensional array, each plate-line driver transistor corresponding to a plate line,

the method comprising:
allowing each tree structure in at least one row to electrically float near a first predetermined voltage;
applying a second predetermined voltage V to a selected plate line;
detecting a potential of each tree structure in the at least one row;
determining whether each detected potential corresponds to a 0 or a 1 for each memory cell at the intersections of the selected plate line and the tree structures in the at least one row;
applying the first predetermined voltage to every tree structure in the at least one row;
and
applying the first predetermined voltage to the selected plate line.

5 more elements

A method for writing data to a previously erased memory device, the memory device including a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction, a three-dimensional memory having a plurality of layers and a plurality of tree structures, each layer having a plurality of memory cells and the tree structures being arranged in a plurality of rows, each tree structure having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, and each branch portion of a tree structure extending from the trunk portion of the tree structure, a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer of the three-dimensional memory, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a memory cell being located at each intersection region in a layer, and a plurality of plate-line driver transistors formed on the substrate and arranged in a two-dimensional array, each plate-line driver transistor corresponding to a plate line,

the method comprising:
applying a voltage V/3 to each tree structure in at least one row of tree structures;
applying a voltage 2V/3 to each plate line in the at least one row of tree structures;
applying a voltage V to a predetermined number of selected tree structures in the at least one row of tree structures;
applying a voltage 0 to a selected plate line where a data “1” will be written in a predetermined number of selected memory cells at the intersection of the first predetermined number of tree structures and the selected plate line;
applying a voltage 2V/3 to the selected plate line;
applying a voltage V/3 to the predetermined number of selected tree structures in the at least one row of tree structures;
applying a voltage 0 to each plate line in the at least one row of tree structures;
and
applying a voltage 0 to each tree structure in the at least one row of tree structures.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/974,749Filed 15 Oct 2007 · division
Priority: 3 Jun 2003
Published: US 2008/0037349 A114 Feb 2008
Granted: 9 Dec 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 11/22
Using electric elements: using ferroelectric elements
G11C 11/5678
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using…

Family

Application10/453,137Parent of this continuation-in-part · filed 3 Jun 2003
Application10/751,740Parent of this division · filed 5 Jan 2004
US 2008/0037349 A1Pre-grant publication · published 14 Feb 2008
US 7,291,878 B2Parent of this division
Application10/751,740Parent of this continuation-in-part
US 2004/0245547 A1Published application
US 7,463,502 B2This patent

From the US filing history. Foreign family members aren’t listed.