Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method

A computer program product comprising a computer-readable storage medium having computer-readable program code embodied in said medium, said computer-readable program code comprising:

• computer-readable program code that generates a core communication graph identifying an electrical interconnection relationship between a plurality of cores to be provided on the integrated circuit chip;
• computer-readable program code that generates a network-on-chip architecture including at least a plurality of switches, a plurality of tiles and a plurality of links interconnecting the plurality of switches;
• and
• computer-readable program code that generates a core-tile-switch mapping architecture on the integrated circuit chip by mapping the plurality of cores to the plurality of tiles using a mapping method, said mapping method comprising:
• multiplying a data communication flow from a first one of the plurality of cores to a second one of the plurality of cores by a hop distance measured between a first one of the plurality of switches and a second one of the plurality of switches, to thereby yield a plurality of multiplication result values;
• and
• summing the plurality of multiplication result values.

A method of creating an optimized core-tile-switch mapping architecture in an on-chip bus, comprising:

• creating a core communication graph representing a connection relationship between arbitrary cores;
• creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches;
• and
• mapping the cores to the tiles using a predetermined optimized mapping method and creating the optimized core-tile-switch mapping architecture,
• wherein the optimized mapping method comprises:
• a first step of multiplying a data communication flow from an arbitrary core s to an arbitrary core d by a hop distance between an arbitrary switch i and an arbitrary switch j, in which the values of the switches i and j are changed to the values of switches surrounding an arbitrary tile k and switches surrounding an arbitrary tile l, the multiplication is carried out for the changed values, and then the multiplication result values are summed up;
• a second step of carrying out the calculation of the first step for all tiles and summing up the result values;
• and
• a third step of multiplying a communication volume from the core s to the core d by the result value of the second step, in which values of the cores s and d are changed to the values of all cores, the multiplication is carried out for the changed values, and the multiplication result values are summed up, to thereby decide the cores s and d which minimize the hop distance between the switches i and j.

A computer-readable recording medium for recording a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus using a core communication graph and a Network-on-chip (NOC) architecture, the method comprising:

• a first step of multiplying a data communication flow from an arbitrary core s to an arbitrary core d by a hop distance between an arbitrary switch i and an arbitrary switch j, in which the values of the switches i and j are changed to the values of switches surrounding an arbitrary tile k and switches surrounding an arbitrary tile l, the multiplication is carried out for the changed values, and then the multiplication result values are summed up;
• a second step of carrying out the calculation of the first step for all tiles and summing up the result values;
• and
• a third step of multiplying a communication volume from the core s to the core d by the result value of the second step, in which values of the cores s and d are changed to the values of all cores, the multiplication is carried out for the changed values, and the multiplication result values are summed up, to thereby decide the cores s and d which minimize the hop distance between the switches i and j.