System and method for aligning a quadrature encoder and establishing a decoder processing speed
AssigneeAvago Technologies ECBU IP (Singapore) Pte. Ltd.
InventorsMoon Leong Low, Han Hua Leong, Wee Sern Lim
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Abstract
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.
Claims19
A method for determining a minimum required processing speed for a logic decoder comprising:
- measuring two or more logic state widths;
- and
- calculating said minimum required processing speed using said widths in combination with a desired number of processing cycles for deciding a logic state.
A method for determining a safety factor of a logic decoder, said decoder having a processing speed, said method comprising:
- measuring two or more logic state widths;
- calculating a logic state width error;
- choosing a number of processing cycles required to decide a logic state;
- and
- calculating said safety factor using said logic state width error, said decoder processing speed and said chosen number of processing cycles.
A system for analyzing logic encoder performance comprising:
- a sampler, for capturing rising and falling edges of logic signals on channels of said encoder;
- logic for determining two or more logic state widths using the said rising and falling edges and determining inequalities between one of said widths and at least one other of said widths;
- logic to calculate logic state width error using said inequalities, and
- logic to calculate a required decoder processing speed using said logic state width error in combination with a desired number of processing cycles for deciding a logic state.
A system for analyzing logic encoder performance comprising:
- a sampler, for capturing rising and falling edges of logic signals on channels of said encoder;
- logic for determining two or more logic state widths using the said rising and falling edges and determining inequalities between one of said widths and at least one other of said widths;
- logic to calculate logic state width error using said inequalities, and
- logic to calculate a decoder safety factor using said logic state width error in combination with a processing speed of said decoder.
Dependencies are inferred from the claim text.