Method and system for improving quality of a circuit through non-functional test pattern identification
AssigneeLSI Corporation
InventorsArun Gunda, Narendra Devta-Prasanna
Life of this patent
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Abstract
The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT faults may be utilized as the first target for the pattern truncation which will reduce the amount of test patterns to be tested. A set of test patterns for functional may be utilized for improving the TDF coverage.
Claims18
A method for selective use of test patterns, comprising steps of:
- providing a total set of test patterns for a circuit;
- detecting transition delay fault (TDF) faults by applying the total set of test patterns;
- identifying a first set of TDF faults and a second set of TDF faults from the TDF faults;
- and
- dividing the total set of test patterns into a first set of test patterns designed to test functional logic and a second set of test patterns designed to test non-functional logic based on the first set of TDF faults and the second set of TDF faults,
- wherein the first set of test patterns is utilized to improve TDF coverage and the second set of test patterns is the first order of test patterns to be pruned if the total set of test patterns fail to fit on a tester.
A computer readable medium containing program instructions for providing quality improvement through selective use of TDF test patterns, the program instructions comprising:
- providing TDF faults on the TDF test patterns for a circuit;
- identifying functional faults from the TDF faults;
- including the functional faults in a first set of TDF faults;
- including remaining faults from the TDF faults in a second set of TDF faults;
- and
- separating a first set of test patterns designed to test functional logic for the first set of TDF faults and a second set of test patterns designed to test non-functional logic for the second set of TDF faults from the TDF test patterns,
- wherein the second set of test patterns is pruned first if a total of the first set of test patterns and the second set of test patterns fail to fit on a tester.
A method for providing quality improvement in ICs, comprising steps of:
- providing a first net list of a circuit;
- providing a second net list of the circuit;
- providing test patterns generated for detecting TDF faults;
- detecting TDF faults through applying the test patterns;
- identifying a first set of test patterns designed to test functional logic and a second set of test patterns designed to test non-functional logic;
- utilizing the first set of test patterns to improve TDF coverage;
- and
- pruning the second set of test patterns first for yield improvement,
- wherein the first net list is a pre-test insertion net list and the second net list is a post-test insertion net list.
Dependencies are inferred from the claim text.