US 7,461,310 B2Granted

IC functional and delay fault testing

AssigneeSpringsoft, Inc.

InventorHsin-Po Wang

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated circuit (IC) tester tests an IC having logic blocks that communicate through clocked devices arranged into scan chains. The tester organizes a low-speed IC functional test into a succession of test cycles, each of a uniform test cycle period, and can clock each clocked device up to once per test cycle with adjustable clock signal edge timing. At selected times during the functional test, the tester executes a capture procedure wherein it adjusts clock signal edge timing so that a delay between clocking of the input and output signals of selected logic blocks is less than the test cycle period to determine whether those logic blocks can operate at high frequency without delay faults. The tester executes a scan procedure immediately following each capture procedure to acquire data representing states of logic block output signals to enable the tester to determine whether one or more selected logic blocks experienced delay faults during the capture procedure.

Claims23

Dependent claims

A method for performing a test on at least one integrated circuit (IC), wherein each IC produces output signals in response to input signals and comprises a plurality of logic blocks and a plurality of clocked devices, wherein the clocked devices of each IC are interconnected to form at least one scan chain, wherein during a normal mode of scan chain operation, the clocked devices forming each scan chain convey data signals between logic blocks of the IC, wherein during a scan mode of scan chain operation, each scan chain provides output state data representing states of the data signals conveyed by the clocked devices forming the scan chain and then sets the data signals to states indicated by input state data, and wherein the test spans a plurality of test cycles of a uniform test cycle period, the method comprising the steps of:

a. selecting at least one of the logic blocks as a delay test block,
b. performing a functional test spanning a plurality of test cycles on each IC by placing each scan chain in its normal mode of operation, by providing the input signals to the IC, by clocking each clocked device of the IC, and by monitoring the IC's output signals to determine whether they are of expected states,
wherein, the functional test includes at least one capture procedure wherein clocking of each clocked device receiving an output data signal of at least one of the delay test blocks follows clocking of each clocked device providing an input data signal to that delay test block with a target delay that is shorter than the test cycle period, and
wherein during other portions of the functional test, clocking of each clocked device receiving an output data signal of any one of the delay test blocks follows clocking of each clocked device providing an input data signal to that delay test block with a target delay that is longer than the target period, and
c. temporarily interrupting the functional test following each capture procedure to carry out a scan procedure by placing each scan chain in the scan mode of operation and acquiring the output state data from the scan chain representing states of the data signals conveyed by the clocked devices at a point when the functional test was interrupted.

2 more elements

A method for testing an integrated circuit (IC) comprising a plurality of logic blocks and a plurality of clocked devices providing paths for data signals passing between the logic blocks to determine whether the logic blocks can operate with the clock devices clocked at their specified clock frequencies, wherein the IC produces IC output signals in response to the data signals, the method comprising the steps of:

a. performing an at-speed first functional test on the IC with its clocked devices clocked at the specified clock frequencies to produce first data indicating states of the IC output signals during a first plurality of test cycles;
b. processing the first data to determine whether it indicates that an IC output signal had a state error during the first functional test;
c. upon determining at step b that an IC output signal had a state error during a test cycle, performing a low-speed second functional test on the IC in which all clocked devices are clocked at rates lower than their specified clock frequencies to produce second data indicating IC output signal states during a second plurality of test cycles;
and
d. following step c, processing the first and second data to determine whether the IC output signal state error during the first functional test resulted from an excessive path delay in at least one of the logic blocks;
and
e. upon determining at step d that an excessive path delay caused the IC output signal state error during the first functional test, performing at least one third functional test on the IC to produce third data indicating IC output signal states during a third plurality of test cycles;
wherein during one portion of each third functional test a capture procedure is executed wherein the clocked devices are clocked at their specified clock frequencies, and
wherein during other portions of the each third functional test the clocked devices are clocked at rates lower than their specified clock frequencies.

6 more elements

Dependencies are inferred from the claim text.