Method for testing semiconductor chips by means of bit masks

A method for testing semiconductor memory chips in which in a chip to be tested which has a test logic, at least one test mode is set, the test mode is executed in the chip and test results or a status of the test mode is output from the chip, comprising:

• providing the chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another;
• storing a first serial bit string, the bit sequence of which can be assigned to at least one test mode, in the first register set;
• transmitting a bit sequence for application of the logical combination between the at least one register of the first register set and the at least one register of the second register set to the first serial bit string stored in the first register set;
• and
• reading out test results or a status of the test mode by means of a second serial bit string.

A method for testing semiconductor memory chips in which in a chip to be tested which has a test logic, at least one test mode is set, the test mode is executed in the chip and test result or a status of the test mode is output from the chip, comprising:

• providing the chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another;
• storing a first serial bit string, the bit sequence of which can be assigned to at least one test mode, in the first register set;
• transmitting a bit sequence for application of the logical combination between the at least one register of the first register set and the at least one register of the second register set to the first serial bit string stored in the first register set;
• and
• reading out test results or a status of the test mode by means of a second serial bit string;
• further comprising providing the first serial bit string with at least one binary check bit, the test logic being controlled by a first check bit which is in a first logic state such that the bits of the first serial bit string which follow the first check bit are skipped until a second check bit which is in a second logic state is detected by the test logic, and the test logic being controlled by the second check bit which is in the second logic state such that the bits of the first serial bit string which follow the second check bit are not skipped until the first check bit which is in the first logic state is detected by the test logic.

A semiconductor chip test system, comprising:

• a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another;
• means for storing a first serial bit string, the bit sequence of which can be assigned to at least one test mode, in the first register set;
• means for transmitting a bit sequence for application of the logical combination between the at least one register of the first register set and the at least one register of the second register set to the first serial bit string stored in the first register set;
• and
• means for reading out test results or a status of the test mode by means of a second serial bit string.