US 7,461,307 B2Granted

System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop

AssigneeLSI Corporation

InventorsArun Gunda, Narendra Devta-Prasanna

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Abstract

The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.

Claims20

Dependent claims

A method for delay fault testing in a circuit, comprising steps of:

providing a scan chain;
selecting a subset of scan flip-flops from said scan chain;
and
replacing said subset of scan flip-flops with a plurality of Enhanced Scan flip-flops, each of said plurality of Enhanced Scan flip-flops comprising a first flip-flop including a first multiplexer, a second flip-flop communicatively coupled to said first flip-flop including a second multiplexer, a functional data input coupled to said first multiplexer and said second multiplexer, a scan input coupled to said first multiplexer, said scan input for receiving signals from an adjacent flip-flop in a scan chain wherein an output of said adjacent scan flip-flop is coupled to said first flip-flop, a SEN (scan enable) control input for providing a SEN signal to said first flip-flop, said SEN control input selecting said first multiplexer of said first flip-flop to provide an input of said first flip-flop with one selected from said functional data input and said scan input, and a ESM control input for providing a ESM signal to said second flip-flop, said ESM control input selecting said second multiplexer of said second flip-flop to provide an input of said second flip-flop with one selected from said functional data input and an output of said first flip-flop,
wherein each of said plurality of Enhanced Scan flip-flops is configurable for operating at least one Enhanced Scan flip-flop mode.

2 more elements

A system for improving test delay fault coverage in a delay fault test of integrated circuits, comprising:

means for providing a scan chain;
means for selecting a subset of scan flip-flops from said scan chain;
and
means for replacing said subset of scan flip-flops with a plurality of Enhanced Scan flip-flops, each of said plurality of Enhanced Scan flip-flops comprising a first flip-flop including a first multiplexer, a second flip-flop communicatively coupled to said first flip-flop including a second multiplexer, a functional data input coupled to said first multiplexer and said second multiplexer, a scan input coupled to said first multiplexer, said scan input for receiving signals from an adjacent flip-flop in a scan chain wherein an output of said adjacent scan flip-flop is coupled to said first flip-flop, a SEN (scan enable) control input for providing a SEN signal to said first flip-flop, said SEN control input selecting said first multiplexer of said first flip-flop to provide an input of said first flip-flop with one selected from said functional data input and said scan input, and a ESM control input for providing a ESM signal to said second flip-flop, said ESM control input selecting said second multiplexer of said second flip-flop to provide an input of said second flip-flop with one selected from said functional data input and an Output of said first flip-flop,
wherein each of said plurality of Enhanced Scan flip-flops includes a first flip-flop and a second flip-flop which are both coupled to a functional data input, content of said first flip-flop is shifted into said second flip-flop during a launch cycle, and said first flip-flop captures a test response during a capture cycle.

2 more elements

An enhanced scan flip-flop for improving a test delay fault coverage for enhanced broadside testing of a circuit, comprising:

a first flip-flop including a first multiplexer;
a second flip-flop communicatively coupled to said first flip-flop including a second multiplexer;
a functional data input coupled to said first multiplexer and said second multiplexer;
a scan input coupled to said first multiplexer, said scan input for receiving signals from an adjacent flip-flop in a scan chain, wherein an output of said adjacent scan flip-flop is coupled to said first flip-flop;
a SEN (scan enable) control input for providing a SEN signal to said first flip-flop, said SEN control input selecting said first multiplexer of said first flip-flop to provide an input of said first flip-flop with one selected from said functional data input and said scan input;
and
a ESM control input for providing a ESM signal to said second flip-flop, said ESM control input selecting said second multiplexer of said second flip-flop to provide an input of said second flip-flop with one selected from said functional data input and an output of said first flip-flop,
wherein content of said first flip-flop is shifted into said second flip-flop during a launch cycle and said first flip-flop captures a test response during a capture cycle.

5 more elements

Dependencies are inferred from the claim text.