Output data compression scheme using tri-state
AssigneeMicron Technology, Inc.
InventorFrankie Fariborz Roohparvar
Life of this patent
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Abstract
A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to a detected read error. Non-compressed internal I/O lines are used during testing to provide control signals to the driver circuitry to selectively place drivers in the tri-state mode. Once a tri-state is detected four columns of memory cells can be replaced with four columns of redundant memory cells without requiring additional non-compressed testing.
Claims19
A memory device comprising:
- sensing circuitry for reading a plurality of stored data bits during a test mode read cycle;
- read compression circuitry for generating a reduced plurality of compressed data bits from the plurality of stored data bits;
- and
- an output circuit coupled to the read compression circuitry to drive a plurality of output signals equal to the plurality of compressed data bits, wherein selected output signals are tri-stated in response to a subset of the plurality of compressed data bits.
A memory device comprising:
- a test circuit adapted to detect first and second patterns among a plurality of stored data bits, wherein the first and second patterns are not all logical ones or logical zeros;
- compression circuitry to compress the plurality of stored data bits to a plurality of compressed data bits in response to the test circuit, the plurality of compressed data bits being less than the plurality of stored data bits;
- and
- a plurality of output drivers corresponding to the plurality of stored data bits, wherein, during a test mode of operation, only a reduced plurality of output drivers transfer the plurality of compressed data bits to a plurality of output nodes, wherein each of the reduced plurality of output drivers is selectively placed in a tri-state mode when the plurality of stored data bits are not in the first or second patterns.
A flash memory device having a test mode of operation, the device comprising:
- compression circuitry to compress a plurality of stored data bits read from a plurality of columns of the flash memory into a reduced quantity of compressed data bits;
- an output driver circuit comprising a plurality of output drivers to output the compressed data bits to a plurality of output nodes;
- and
- a data bus coupled between the compression circuitry and the output driver circuit, wherein each of the plurality of output drivers are individually and selectively placed in a tri-state mode in response to a command provided on a subset of the data bus that is unused by the compressed data bits.
A method for testing an integrated circuit memory comprising:
- reading a plurality of stored data bits from a plurality of outputs of sensing circuitry in the memory;
- and
- compressing the plurality of stored data bits to generate a plurality of compressed data bits such that the plurality of compressed bits are output as a plurality of output bits that are either a logic one or a logic zero in response to the plurality of compressed data bits or one or more of the plurality of output bits is individually tri-stated in response to a command code.
A method for testing an integrated circuit memory comprising:
- reading a plurality of outputs of sensing circuitry in the memory so that a plurality of stored data bits are read;
- comparing the plurality of stored data bits to a predetermined data pattern;
- compressing the plurality stored data bits to a reduced quantity of a plurality of compressed data bits;
- coupling the plurality of compressed data bits to an output driver circuit via a plurality of lines of an internal bus;
- and
- generating a plurality of output data bits from the output driver circuit in response to the plurality of compressed data bits and the comparison, wherein each of the plurality of output data bits is selectively tri-stated in response to a command code.
A memory test system comprising:
- a memory tester;
- a plurality of memory integrated circuits coupled to the memory tester, each of the memory integrated circuits comprising:
- sensing circuitry for reading a plurality of stored data bits;
- and
- read compression circuitry for generating for compressing the plurality of stored data bits to a reduced plurality of compressed data bits;
- and
- an output circuit coupled to the read compression circuitry for driving a plurality of output signals, wherein the plurality of output signals are either a logic one or a logic zero in response to the plurality of compressed data bits or the plurality of output bits are selectively tri-stated in response to a command code.
Dependencies are inferred from the claim text.