System and method for detecting and preventing race condition in circuits

A method for detecting race conditions comprising:

• receiving a data stream by a first memory element, wherein the first memory element is part of a plurality of memory elements sorted in sequence;
• receiving the output from the first memory element by each additional memory element other than the first memory element;
• delaying data stream propagation between the first memory element and the plurality of additional memory elements starting with a third memory element using delay elements, wherein a memory element of order n receives the output from the first memory element after passing through (n−2) delay elements, wherein all of the delay elements introduce a same amount of time delay;
• comparing the data stream and an output of each of the plurality of additional memory elements;
• and
• identifying whether a race condition is present between the first memory element and any one of the plurality of additional memory elements based on the comparison.

A circuit for determining a degree of buffering required along a data

• bus to avoid race conditions, comprising:
• circuit means for receiving a data stream by a first memory element, wherein the first memory element is part of a plurality of memory elements sorted in sequence;
• circuit means for receiving the output from the first memory element by each additional memory element other than the first memory element;
• circuit means for delaying data stream propagation between the first memory element and the plurality of additional memory elements starting with a third memory element using delay elements, wherein a memory element of order n receives the output from the first memory element after passing through (n−2) delay elements, wherein all of the delay elements introduce a same amount of time delay;
• circuit means for comparing the data stream and an output of each of the plurality of additional memory elements;
• and
• circuit means for identifying whether a race condition is present between the first memory element and any one of the plurality of additional memory elements based on the comparison.