Integrated circuit test using clock signal modification
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorEitan Rosen
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Abstract
An apparatus, method, and computer program for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising a control circuit adapted to provide a control signal; and a signal generator adapted to receive a first clock signal comprising k pulses each having a first duration, change the duration of each of m of the pulses to a second duration in response to the control signal, wherein m<k and the second duration is not substantially equal to the first duration, to produce a second clock signal, and apply the second clock signal to the clock inputs of the plurality of clocked storage elements.
Claims90
An apparatus for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising:
- a control circuit that provides a control signal;
- a signal generator that
- receives a first clock signal comprising k pulses each having a first duration,
- changes the duration of m selected pulses to a second duration in response to the control signal, wherein m<k and the second duration is not substantially equal to the first duration, to produce a second clock signal, and
- applies the second clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- an analysis circuit that identifies one of the signal paths as flawed based on the change of the duration to the second duration.
An apparatus for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising:
- control means for providing a control signal;
- signal generator means for
- receiving a first clock signal comprising k pulses each having a first duration,
- changing the duration of m selected pulses to a second duration in response to the control signal, wherein m<k and the second duration is not substantially equal to the first duration, to produce a second clock signal, and
- applying the second clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- analysis means for identifying one of the signal paths as flawed based on the change of the duration to the second duration.
A method for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the method comprising:
- receiving a first clock signal comprising k pulses each having a first duration;
- changing the duration of m selected pulses to a second duration in response to the control signal, wherein m<k and the second duration is not substantially equal to the first duration, to produce a second clock signal;
- applying the second clock signal to clock inputs of a plurality of clocked storage elements interconnected by a plurality of signal paths in a circuit, and
- identifying one of the signal paths as flawed based on the change of the duration to the second duration.
A computer readable medium encoded with a computer program embodying instructions executable by a computer to perform a method for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the method comprising:
- receiving a first clock signal comprising k pulses each having a first duration;
- changing the duration of m selected pulses to a second duration in response to the control signal, wherein m<k and the second duration is not substantially equal to the first duration, to produce a second clock signal;
- applying the second clock signal to clock inputs of a plurality of clocked storage elements interconnected by a plurality of signal paths in a circuit, and
- identifying one of the signal paths as flawed based on the change of the duration to the second duration.
An apparatus for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising:
- a control circuit that provides a control signal;
- a signal generator that
- produces a clock signal that includes k pulses, the k pulses comprising j pulses each having the first duration and m selected pulses having a second duration in response to the control signal, wherein k=m+j, and wherein the second duration is not substantially equal to the first duration, and
- applies the clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- an analysis circuit that identifies one of the signal paths as flawed based on the second duration.
An apparatus for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the apparatus comprising:
- control means for providing a control signal;
- signal generator means for
- producing a clock signal that includes k pulses, the k pulses comprising j pulses each having the first duration and m selected pulses having a second duration in response to the control signal, wherein k=m+j, and wherein the second duration is not substantially equal to the first duration, and
- applying the clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- analysis means for identifying one of the signal paths as flawed based on the second duration.
A method for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the method comprising:
- receiving a control signal;
- producing a clock signal comprising k pulses including j pulses each having a first duration and m selected pulses having a second duration in response to the control signal, wherein k=m+j, and wherein the second duration is not substantially equal to the first duration;
- applying the clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- identifying one of the signal paths as flawed based on the second duration.
The computer readable medium embodying instructions executable by a computer to perform a method for testing an integrated circuit comprising a plurality of clocked storage elements each having a clock input, wherein the clocked storage elements are interconnected by a plurality of signal paths, the method comprising:
- receiving a control signal;
- producing a clock signal comprising k pulses including j pulses each having a first duration and m selected pulses having a second duration in response to the control signal, wherein k=m+j, and wherein the second duration is not substantially equal to the first duration;
- applying the clock signal to the clock inputs of the plurality of clocked storage elements;
- and
- identifying one of the signal paths as flawed based on the second duration.
Dependencies are inferred from the claim text.