Timing failure analysis in a semiconductor device having a pipelined architecture

A method of testing a semiconductor device having a pipelined architecture, the method comprising:

• disabling operation of a first pipeline stage of the semiconductor device during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device;
• executing a second pipelined operation to enable the second pipeline stage to generate an intermediate result using the test data;
• and
• evaluating a final result of the second pipelined operation to determine whether the second pipeline stage produced a correct intermediate result, further comprising operating a third pipelined operation prior to the first pipelined operation to generate the test data at an output of the first pipeline stage, the output of the first pipeline stage being coupled to the input of the second pipeline stage.

A method of testing a semiconductor device having a pipelined architecture, the method comprising:

• disabling operation of a first pipeline stage of the semiconductor device during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device;
• executing a second pipelined operation to enable the second pipeline stage to generate an intermediate result using the test data;
• evaluating a final result of the second pipelined operation to determine whether the second pipeline stage produced a correct intermediate result;
• and
• delaying a control signal used to initiate the second pipelined operation if the final result does not match an expected result, wherein delaying the control signal effects an increase in a setup time at the input of the second pipeline stage, and wherein the disabling operation enables the test data to remain in a substantially steady-state at the input of the second pipeline stage for an extended period of time.

A method of testing a semiconductor device having a pipelined architecture, the method comprising:

• disabling operation of a first pipeline stage of the semiconductor device during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device;
• executing a second pipeline operation to enable the second pipeline stage to generate an intermediate result using the test data;
• and
• evaluating a final result of the second pipelined operation to determine whether the second pipeline stage produced a correct intermediate result, wherein the disabling operation comprises executing the first pipelined operation to establish data at an input of the first pipeline stage that will, during execution of the second pipelined operation, cause the data at the input of the second pipeline stage to transition from a first data state to a second data state.

A semiconductor device comprising:

• a plurality of pipelined logic stages coupled to one another;
• a control circuit to receive an instruction to perform a pipelined operation within the plurality of pipelined logic stages, the control circuit including a timing circuit to output a plurality of control signals to the plurality of pipelined logic stages to initiate operation of each of the pipelined logic stages at an appropriate time;
• and
• a first programmable circuit to store a plurality of enable values and which is coupled to the timing circuit to selectively enable the timing circuit to output each of the plurality of control signals according to the state of a respective one of the plurality of enable values,
• wherein at least one pipelined logic stage comprises a content addressable memory array and wherein the pipelined operation comprises a comparison with a search data value with contents of the content addressable memory array.

A semiconductor device comprising:

• a plurality of pipelined logic stages coupled to one another;
• a control circuit to receive an instruction to perform a pipelined operation within the plurality of pipelined logic states, the control circuit including a timing circuit to output a plurality of control signals to the plurality of pipelined logic stages to initiate operation of each of the pipelined logic stages at an appropriate time;
• a first programmable circuit to store a plurality of enable values and which is coupled to the timing circuit to selectively enable the timing circuit to output each of the plurality of control signals according to the state of a respective one of the plurality of enable values;
• and
• a second programmable circuit to store a plurality of delay control values each to determine a time at which a corresponding one of the plurality of control signals is output by the timing circuit.

A semiconductor device comprising:

• a plurality of pipeline stages coupled to one another;
• means for disabling operation of a first pipeline stage of the plurality of pipeline stages during a first pipelined operation to establish test data at an input of a second pipeline stage of the plurality of pipeline stages;
• means for executing a second pipelined operation to enable the second pipeline stage to generate an intermediate result using the test data;
• and
• means for evaluating a final result of the second pipelined operation to determine whether the second pipeline stage produced a correct intermediate result, wherein the semiconductor device comprises a content addressable memory array and wherein executing the second pipelined operation comprises searching the content addressable memory array to determine if contents thereof match a search value.