US 7,461,287 B2Granted

Elastic interface de-skew mechanism

AssigneeInternational Business Machines Corporation

InventorsDaniel M. Dreps, Frank D. Ferraiolo, Gary A. Peterson, Robert J. Reese

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Abstract

A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

Claims17

Dependent claims

A method of inter-chip communication comprising the steps of:

launching a first clock signal from a first chip;
launching a first data signal from the first chip, wherein the first data signal comprises a plurality of first data beats;
launching a second data signal from the first chip, wherein the second data signal comprises a plurality of second data beats, wherein the plurality of first data beats are sent substantially concurrently with corresponding beats of the plurality of second data beats;
receiving the first clock signal to result in a received first clock signal;
receiving the first data signal to result in a received first data signal;
receiving the second data signal to result in a received second data signal;
delaying the received first data signal by less than a bit time by using at least a first variable delay line to align one or more of the centers of the plurality of first data beats with a first closest edge, wherein the first closest edge is related to an edge of the received first clock signal resulting in a delayed, received first signal;
delaying the received second data signal by less than the bit time by using at least a second variable delay line to align one or more of the centers of the plurality of the second data beats with a second closest edge, wherein the second closest edge is related to another edge of the received first clock signal, wherein delaying the received second signal results in a delayed, received second signal;
determining a first needed delay time for further delaying the delayed, received first data signal;
and
further delaying the delayed, received first data signal by the first needed delay time using latches.

8 more elements

A circuit for receiving digital signals, the circuit comprising:

(a) a variable data delay line, wherein the variable data delay line comprises a functional tap, a setup tap, and an alternate delay tap;
(b) a clock receiver for receiving a bus clock associated with a data group, wherein the data group comprises a plurality of data streams, wherein the bus clock comprises timing information for the plurality data streams;
(c) a clock delay line, wherein the clock delay line is for generating an I/O clock from the bus clock, wherein the clock delay line is for generating a guardband delayed clock from the bus clock;
(d) a functional sampler, wherein the functional sampler latches data from the functional tap in response to the I/O clock;
(e) an alternate sampler, wherein alternate sampler latches data from the alternate delay tap in response to the I/O clock;
(f) a setup sampler, wherein the setup sampler latches data from the setup tap in response to the I/O clock;
(h) a hold-time sampler, wherein the hold-time sampler latches data from the functional tap in response to the guardband delayed clock;
(i) first logic circuitry for detecting a reference beat in an interface alignment pattern;
and
(j) a first multiplexer for selecting between a functional sampler output, an alternate sampler output, or a setup sampler output.

7 more elements

A method of aligning an elastic interface bus, the method comprising the steps of:

storing a first received data bit in a variable delay line, wherein the variable delay line has a number X positions;
setting a functional delay variable to a first value, wherein the functional delay variable affects the relative position of a sampling group within the variable delay line, wherein the sampling group has a hold sample point a number Y positions from a functional sample point;
wherein the sampling group has a setup sample point substantially Y positions from the functional sample point;
setting a guardband delay value to second value, wherein the guardband delay value affects the value Y;
(a) retrieving a plurality of functional samples;
(b) retrieving a plurality of hold samples;
(c) retrieving a plurality of setup samples;
(d) comparing the pluralities of functional, hold, and setup samples to each other to detect whether there are a threshold number of data mis-compares;
(e) if there are a threshold number of data mis-compares, incrementing the functional delay variable to change the relative position of the sampling group within the variable delay line and performing the substeps of:
(i) repeating steps (a) through (e) until there are less than the threshold number of data mis-compares;
or
(ii) repeating (a) through (e) to result in sampling over substantially all of the X positions of the variable delay line, and if there is greater than the threshold number of data mis-compares, then decrementing the guardband delay value to decrease Y and repeating steps (a) through (e) until there are less than the threshold number of data mis-compares.

9 more elements

Dependencies are inferred from the claim text.