Back to results
US 7,461,285 B2Granted
Programmable resistor array having current leakage control
AssigneeSilicon Laboratories Inc.
InventorLouis J. Nervegna
Life of this patent
Estimating the term…
Abstract
A free running clock circuit includes a programmable resistor array including a plurality of resistors connected in series. A plurality of transistors are connected to the plurality of resistors wherein each of the plurality of resistors has one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor and providing a resistance thereto. A transistor funnel limits leakage currents from a portion of the plurality of transistors to a single transistor of the transistor funnel.
Claims27
A free running clock circuit, comprising:
- a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an inherent temperature profile associated therewith;
- and
- a voltage divider circuit for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit, the voltage divider circuit having a top programmable resistor array connected in series with at least two programmable resistor arrays connected in parallel between two supply terminals of differing voltages;
- a first programmable resistor array of said at least two programmable resistor comprising:
- a plurality of resistors connected in series;
- a plurality of transistors, each of the plurality of resistors having one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor array and providing a resistance thereto;
- a transistor funnel for limiting leakage currents from a plurality of portions of the plurality of transistors to a single transistor of the transistor funnel.
4 more elements
An integrated system on a chip with serial asynchronous communication capabilities, comprising:
- processing circuitry for performing predefined digital processing functions on the chip;
- a free running clock circuit for generating a temperature compensated clock, comprising:
- a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an inherent temperature profile associated therewith;
- and
- a voltage divider circuit for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit, the voltage divider circuit having a top programmable resistor array connected in series with at least two programmable resistor arrays connected in parallel between two supply terminals of differing voltages;
- a first programmable resistor array of said at least two programmable resistor comprising:
- a plurality of resistors connected in series;
- a plurality of transistors, each of the plurality of resistors having one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor array and providing a resistance thereto;
- a transistor funnel for limiting leakage currents from a plurality of portions of the plurality of transistors to a single transistor of the transistor funnel;
- an asynchronous on-chip communication device for digitally communicating with an off-chip asynchronous communication device, which off-chip asynchronous communication device has an independent time reference, which communication between said on-chip communication device and said off-chip asynchronous communication device is effected without clock recovery, said asynchronous on-chip communication device having a time-base derived from said temperature compensated clock;
- and
- wherein said temperature compensated clock provides a time reference for both said processing circuitry and said asynchronous on-chip communication device.
9 more elements
A free running clock circuit, comprising:
- a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an inherent temperature profile associated therewith;
- and
- a voltage divider circuit for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit, the voltage divider circuit having a top programmable resistor array connected in series with at least two programmable resistor arrays connected in parallel between two supply terminals of differing voltages;
- a second programmable resistor array of the at least two programmable resistor arrays, comprises:
- a second plurality of resistors connected in parallel;
- a plurality of low leakage transistors, each of the plurality of resistors having one of the plurality of low leakage transistors associated therewith for connecting a resistor to the second programmable resistor array and providing a resistance thereto;
- and
- wherein each of the low leakage transistors have a negative gate source voltage when the low leakage transistor is in an off state.
5 more elements
Dependencies are inferred from the claim text.