Dynamic core swapping
AssigneeIntel Corporation
InventorsBrian V. Belmont, Animesh Mishra, James P. Kardach
Life of this patent
Estimating the term…
Abstract
An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
Claims20
An apparatus comprising:
- a first core having a first instruction set to execute a program at a first performance level, the first core stopping executing the program when a triggering event occurs;
- a second core having a second instruction set compatible with the first instruction set and having a second performance level different than the first performance level, the second core being in a power down state when the first core is executing the program, the first and second cores being in a dynamic multi-core unit;
- and
- a circuit coupled to the first and second cores to power up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
A method comprising:
- executing a program at a first performance level by a first core having a first instruction set,
- stopping executing the program by the first core when a triggering event occurs;
- powering up a second core after the first core stops executing the program, the second core having a second instruction set compatible with the first instruction set and having a second performance level different than the first performance level, the second core being in a power down state when the first core is executing the program, the first and second cores being in a dynamic multi-core unit;
- and
- continuing executing the program at the second performance level by the second core.
A system comprising:
- a memory to store a program;
- and
- a multi-core processor coupled to the memory to execute the program at different performance levels and different power levels, the processor comprising:
- a first core having a first instruction set to execute the program at a first performance level, the first core stopping executing the program when a triggering event occurs,
- a second core having a second instruction set compatible with the first instruction set and having a second performance level different than the first performance level, the second core being in a power down state when the first core is executing the program, the first and second cores being in a dynamic multi-core unit, and
- a circuit coupled to the first and second cores to power up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
Dependencies are inferred from the claim text.