Method and apparatus for providing context switching of logic in an integrated circuit using test scan circuitry
AssigneeATI Technologies ULC
InventorsMark S. Grossman, Gregory C. Buchner
Life of this patent
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Abstract
A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit includes context control logic operative to control the test scan circuit to at least one of: store and restore context state information contained in functional storage elements in response to detection of a request for a change in context during normal operation of the integrated circuit.
Claims23
A method for providing context switching in an integrated circuit comprising:
- detecting a request for a change in context for at least one of a plurality of logic circuits in the integrated circuit;
- controlling at least one test scan circuit and at least one RAM wrapper associated with the at least one of the logic circuits to at least one of:
- save and restore context state information of the at least one of the logic circuits in response to the request for a change in context;
- and wherein context state information comprises data stored in flip flops and in RAM elements, said RAM elements being operated in a functional mode and wherein at least one RAM element corresponds to said RAM wrapper;
- and
- storing said context state information in a context state information storage memory.
An integrated circuit comprising:
- at least one test scan circuit and at least one RAM wrapper operative to use test data during a test mode and operatively coupled to use non-test data during normal operation;
- context control logic operative to control the test scan circuit to at least one of:
- store and restore context state information of the test scan circuit in response to detection of a request for a change in context during normal operation;
- context state information storage memory operatively coupled to said context control logic and said at least one test scan circuit and operative to store from, and restore to, said at least one test scan circuit, said context state information;
- and
- wherein the test scan circuit comprises a plurality of scan chains wherein at least one of the scan chains comprises:
- latch elements and at least one random access memory array and wherein the context control logic is operative to select inputs to each of the plurality of scan chains to facilitate restoring of the context state information from said context state information storage memory during non-test operation.
An integrated circuit comprising:
- at least one test scan circuit associated with at least one logic circuit, said at least one test scan circuit comprising parallel scan chains of at least latch elements, at least one RAM wrapper and at least one random access memory array;
- context control logic operative to control the test scan circuit to at least one of:
- save and restore context state information of the at least one logic circuit in response to the detection of a request for a change in context during non-test operation of the at least one logic circuit;
- and
- context state information storage memory operatively coupled to said context control logic and said at least one test scan circuit and operative to store from, and restore to, said at least one test scan circuit, said context state information.
An integrated circuit comprising:
- at least one random access memory array;
- at least one test scan circuit operatively coupled to the RAM array and operative to test the RAM array during a test mode;
- at least one RAM wrapper operative to use test data during a test mode and operatively coupled to use non-test data during normal operation;
- context control logic operative to control the test scan circuit to at least one of:
- store and restore context information from and to the RAM array, in response to the detection of a change in context during non-test operation of the RAM array;
- and
- context state information storage memory operatively coupled to said context control logic and said at least one test scan circuit and said at least on RAM array and operative to store from, and restore to, said at least one test scan circuit and said RAM array, said context state information.
Dependencies are inferred from the claim text.