Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines

A method, in a data processing device having an instruction pipeline and a load/store pipeline, for processing load instructions, comprising:

• receiving a load instruction;
• associating the load instruction with a load tag (LTAG);
• issuing the load instruction and the LTAG to the load/store pipeline;
• attempting to retrieve data corresponding to the load instruction from a first cache;
• determining whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss;
• generating an entry in a load table data structure of a load target buffer based on the LTAG and results of the attempt to retrieve data corresponding to the load instruction;
• issuing the load instruction and the LTAG to the instruction pipeline;
• issuing the load instruction from the instruction pipeline to the load target buffer;
• identifying an entry in the load table corresponding to the issued load instruction based on the LTAG associated with the issued load instruction;
• and
• determining whether to store the data corresponding to the load instruction in a register file based on whether the identified entry in the load table is marked as a cache miss or a cache hit.

An apparatus, comprising:

• an issue unit;
• an instruction pipeline coupled to the issue unit;
• a load/store pipeline coupled to the issue unit;
• a load target buffer coupled to the instruction pipeline and the load/store pipeline;
• and
• a load miss queue unit coupled to the load/store pipeline, wherein:
• the issue unit receives a load instruction, associates the load instruction with a load tag (LTAG), and issues the load instruction and the LTAG to the load/store pipeline,
• the load/store pipeline attempts to retrieve data corresponding to the load instruction from a first level cache and determines whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss, and
• the load target buffer generates an entry in a load table data structure of the load target buffer based on the LTAG and results of the attempt to retrieve data corresponding to the load instruction,
• the load target buffer generates an entry in the load table data structure by:
• generating an entry in the load table that is indexed by the LTAG associated with the load instruction;
• and
• marking the entry as a cache hit or a cache miss based on results of determining whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss, and wherein if the results of determining are a cache miss, the load miss queue recycles the data corresponding to the load instruction from a second level cache and stores the recycled data in the entry in the load table of the load target buffer.

An apparatus, comprising:

• an issue unit;
• an instruction pipeline coupled to the issue unit;
• a load/store pipeline coupled to the issue unit;
• and
• a load target buffer coupled to the instruction pipeline and the load/store pipeline, wherein:
• the issue unit receives a load instruction, associates the load instruction with a load tag (LTAG), and issues the load instruction and the LTAG to the load/store pipeline,
• the load/store pipeline attempts to retrieve data corresponding to the load instruction from a first level cache and determines whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss,
• the load target buffer generates an entry in a load table data structure of the load target buffer based on the LTAG and results of the attempt to retrieve data corresponding to the load instruction;
• the issue unit issues the load instruction and the LTAG to the instruction pipeline,
• the instruction pipeline issues the load instruction to the load target buffer, and
• the load target buffer identifies an entry in the load table corresponding to the issued load instruction based on the LTAG associated with the issued load instruction and determines whether to store the data corresponding to the load instruction in a register file based on whether the identified entry in the load table is marked as a cache miss or a cache hit.