Loosely-biased heterogeneous reconfigurable arrays

A reconfigurable device comprising:

• a plurality of first processing elements of a first processing element type;
• a plurality of second processing elements of a second processing element type;
• a general purpose routing network connected to each of the pluralities of first and second processing elements and adapted to route a signal from any one of the pluralities of first or second processing elements to any other of the pluralities of first or second processing elements;
• a first special-purpose routing network connected to the plurality of first processing elements and configured to cascade, in width across a data path, the plurality of first processing elements, such that the plurality of first processing elements have the same logical function as a single processing element of the first processing element type, having an aggregate data path width corresponding to a width of the plurality of first processing devices;
• and
• a second special-purpose routing network connected to the plurality of second processing elements and adapted to cascade, in width across a data path, the plurality of second processing elements, such that the plurality of second processing elements have the same logical function as a single processing element of the second processing element type, having an aggregate data path width corresponding to a width of the plurality of second processing devices.

A reconfigurable device comprising:

• a plurality of processing elements;
• a first routing network comprising a first physical bit width and a first processing element connection connected to a first one of the plurality of processing elements;
• a second routing network comprising a second physical bit width, narrower than the first physical bit width, and a second processing element connection connected to a second one of the plurality of processing elements;
• and
• a programmable selector comprising an input of the first physical bit width connected to the first routing network and an output of the second physical bit width connected to the second routing network;
• wherein the programmable selector is configured to receive at the input an input signal of the first physical bit width from the first routing network, and to provide on the output an output signal of the second physical bit width to the second routing network, the output signal comprising one or more bits of the input signal.

A reconfigurable device comprising:

• a plurality of processing elements;
• a first routing network comprising a first physical bit width and a first processing element connection connected to a first one of the plurality of processing elements;
• a second routing network comprising a second physical bit width, wider than the first bit width, and a second processing element connection connected to a second one of the plurality of processing elements;
• and
• a programmable selector comprising an input of the first physical bit width connected to the first routing network and an output of the second physical bit width connected to the second routing network;
• wherein the programmable selector is configured to receive at the input an input signal of the first physical bit width from the first routing network, and to provide on the output an output signal of the second physical bit width to the second routing network, the output signal comprising one or more bits of the input signal.

A method of routing a plurality of signals, each signal having a signal bit width, across a reconfigurable device, comprising:

• receiving the plurality of signals at a merge selector at a first location within the reconfigurable device, the plurality of signals having a combined bit width totaling a first bit width, the combined bit width comprising a sum of the signal bit widths of the plurality of signals;
• merging the plurality of signals into a composite signal having a bit width of at least the first bit width using a merge selector;
• routing the composite signal to a second location within the reconfigurable device, over a routing network having a bit width of at least the first bit width;
• receiving the composite signal at a demerge selector at the second location within the reconfigurable device;
• and
• demerging the composite signal of the first bit width into the plurality of signals, each having the signal bit width of the corresponding one of the plurality of signals received at the merge selector.

A reconfigurable device, comprising:

• a first routing network comprising a plurality of routing network inputs and a plurality of routing network outputs;
• a second routing network, comprising a plurality of selectors and a plurality of selector links, each of the selector links connecting two of the plurality of selectors together;
• and
• a plurality of clusters each comprising a plurality of processing elements, each cluster connected to the first routing network and the second routing network;
• wherein each cluster comprises a first processing element of a first processing element type and a second processing element of a second processing element type,
• wherein the first processing element of the first processing element type in a first cluster of the plurality of clusters provides a control input to the second processing element of the second processing element type in a second cluster of the plurality of clusters, the control input being routed via a first selector of the plurality of selectors, a selector link, and a second selector of the plurality of selectors;
• and
• wherein the first routing network comprises a reconfigurable network.