Back to results
US 7,461,218 B2Granted
Size-based interleaving in a packet-based link
AssigneeIntel Corporation
InventorsSridhar Muthrasanallur, Jeff Wilder, Chitra Natarajan
Life of this patent
Estimating the term…
Abstract
A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.
Claims20
A method, comprising:
- receiving a memory read request at a port from a device, wherein the port is connected to the device by a packet-based link;
- enqueuing the memory read request into a small request queue or a large request queue based on an amount of data requested in the memory read request and a data size threshold that is user programmable;
- and
- interleave dequeuing of memory read requests between the small request queue and the large request queue based on a programmable interleave granularity.
1 more element
An article of manufacture comprising:
- a machine-accessible medium including a plurality of instructions which when executed perform operations comprising:
- receiving a memory read request at a port from a device, wherein the port is connected to a port of the device by a packet-based link;
- enqueuing the memory read request into a small request queue or a large request queue based on an amount of data requested in the memory read request;
- and
- interleave dequeuing of memory read requests between the small request queue and the large request queue based on an interleave granularity, wherein the interleave granularity includes a total amount of data requested by dequeued memory read requests before switching between the small request queue and the large request queue.
2 more elements
A computer system, comprising:
- a processor;
- a memory controller hub coupled to the processor;
- one or more Synchronized Dynamic Random Access Memory (SDRAM) units coupled to the memory controller hub;
- a device coupled to the memory controller hub by a packet-based link;
- a non-volatile storage coupled to the memory controller hub via an input/output controller hub, wherein the non-volatile storage including a plurality of instructions which when executed by the processor perform operations comprising:
- receiving a memory read request at a memory controller port of the memory controller hub from the device;
- enqueuing the memory read request into a small request queue or a large request queue at the memory controller hub based on an amount of data requested in the memory read request;
- and
- interleave dequeuing of memory read requests between the small request queue and the large request queue based on an interleave granularity, wherein the interleave granularity includes a total amount of data requested by dequeued memory read requests before switching between the small request queue and the large request queue.
6 more elements
Dependencies are inferred from the claim text.