Advanced processor with implementation of memory ordering on a ring based data movement network

An advanced processor having a plurality of processor cores configured to execute multiple threads and a data switch interconnect (DSI), the DSI being configured to support a memory ordering, the DSI comprising:

• a plurality of ring elements, the ring elements coupled together via a plurality of rings;
• a first bridge coupled to a first memory and the plurality of ring elements, the first bridge having a first ring element corresponding to one of the processor cores;
• and
• a second bridge coupled to a second memory and the plurality of ring elements, the second bridge having a second ring element corresponding to another one of the processor cores;
• wherein each ring element includes:
• a first flip-flop configured to receive a ring input and to provide a first signal to a second flip-flop, a third flip-flop, and a first multiplexer;
• and
• a second multiplexer configured to receive a second signal from a fourth flip-flop and a third signal from a fifth flip-flop and to provide a fourth signal to the first multiplexer, the first multiplexer being configured to provide a ring output.

A means for controlling a flow of packets, comprising:

• a means for placing a request for data on a request ring, the request ring being one of a plurality of rings coupling a plurality of ring elements together;
• a means for checking for the data in each of the plurality of processor cores;
• a means for receiving the request in a memory bridge coupled to the request ring and having at least one of the plurality of ring elements;
• a means for placing the data on a data ring to support a memory ordering, the data ring being one of the plurality of rings;
• and
• a means for acknowledging, on a response ring, the placement of the data on the data ring, the response ring being one of the plurality of rings and being separate from the data ring;
• wherein each ring element includes:
• a first flip-flop configured to receive a ring input and to provide a first signal to a second flip-flop, a third flip-flop, and a first multiplexer;
• and
• a second multiplexer configured to receive a second signal from a fourth flip-flop and a third signal from a fifth flip-flop and to provide a fourth signal to the first multiplexer, the first multiplexer being configured to provide a ring output.