Advanced processor system using request, data, snoop, and response rings

A method of providing a snoop based cache coherency over a ring-based communication network configured to transmit a set of packets among a set of elements in an advanced processor system, the advanced processor system including a plurality of processor cores on a chip wherein the set of elements includes at least the plurality of processor cores, at least one L2 cache connected to said cores, and a memory bridge, the method comprising:

• passing a request packet over the ring-based communication network for data from the set of elements;
• checking each of the set of elements for the data;
• passing a snoop packet over the ring-based communication network to determine whether the set of elements owns the data, wherein if the snoop packet determines that one of the set of elements owns the data,
• providing a snoop acknowledgement which designates which of the set of elements owns the data wherein the snoop based cache coherency is achieved;
• passing a data packet over the ring-based communication network, the data packet including at least the data requested by the request packet;
• and
• passing a response packet over the ring-based communication network by the one of the set of elements that owns the data to provide a response acknowledgement;
• wherein the request packet, the snoop packet, and the data packet travel over three physically separate ring communication channels.

A ring-based data switch interconnect (DSI) device for a single-chip multiple-core processor;

• said single-chip multiple-core processor also having a memory bridge and at least one L2 cache;
• cores of the single-chip multi-core processor being CPU cores that are connected to said at least one L2 cache, said DSI device comprising:
• a request ring with interfaces to said CPU cores and said memory bridge;
• a data ring with interfaces to said CPU cores and said memory bridge;
• a response ring with interfaces to said CPU cores and said memory bridge;
• a snoop ring with interfaces to said CPU cores and said memory bridge;
• a data ring component corresponding to the data ring configured to pass a data portion of a set of packets among a set of ring elements, the data ring component including,
• a data ring input interface,
• a data ring output interface, and
• a data valid bit-input interface;
• and
• a snoop ring component corresponding to the snoop ring configured to pass a snoop packet among the set of ring elements, the snoop ring component including,
• a snoop ring input interface,
• a snoop ring output interface, and
• a snoop valid bit input interface, wherein the snoop ring component is configured to provide a snoop based cache coherency by designating an owner of requested data, and wherein each ring component is a ring structure;
• wherein said CPU cores and said memory bridge are interfaced together in a ring topology for each of said request ring, data ring, response ring, and snoop ring, and said request ring, said data ring, said response ring, and said snoop ring are separate from each other;
• wherein said cores submit data packet read or write requests to said request ring;
• wherein said cores and said memory bridge also inspect said request ring for read or write requests;
• wherein said memory bridge also inspects said response ring for compliance with said requests;
• wherein if a core determines that it can process said read or write requests from data located in its L2 cache, said core places a packet containing requested data on said data ring and places an acknowledgement packet on said response ring or writes said data into its L2 cache and places an acknowledgment packet on said response ring;
• wherein if said memory bridge determines that no core has responded, said memory bridge writes said data to higher latency memory or retrieves said data from the higher latency memory and places said data on said data ring as a data packet.