Circuitry and method for accessing an associative cache with parallel determination of data and data availability

A circuit for accessing an associative cache, comprising:

• data selection circuitry in communication with the associative cache;
• an outcome parallel processing circuit in communication with the associative cache, the outcome parallel processing circuit being configured to determine in parallel whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict, wherein the data selection circuitry and the outcome parallel processing circuit operate in parallel;
• and
• a first memory in communication with the data selection circuitry and the outcome parallel processing circuit, the first memory being configured to store a bank select table, the bank select table being configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data.

A method for accessing an associative cache, comprising method operations of:

• a. receiving a request for data in the associative cache, the request including an address of the data;
• b. accessing out the data at the address of the associative cache;
• c. reading an entry from a bank select table based on the address of the data, the entry defining a first selection of one of a plurality of banks of the associative cache to output the data;
• d. determining whether the accessing out the data is one of a cache hit, a cache miss, or a cache mispredict;
• e. providing a least recently used replacement table, the least recently used replacement table being configured to include entries that define one of the plurality of banks of the associative cache to be replaced on a cache miss;
• and
• f. replacing a slice of the least recently used replacement table on a cache access with entries that define a second selection of one of the plurality of banks that is less recently used, wherein the slice is defined as one of an entire column or an entire row of the least recently used replacement table if the associative cache is defined by two banks,
• wherein the method operations b, c, and d are processed in parallel.