Methods and apparatus for controlling hierarchical cache memory

An apparatus, comprising:

• a first level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the first level cache memory being operable to store an address tag and data, and each cache line having an index associated therewith;
• a next lower level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the next lower level cache memory being operable to store an address tag, status flags, and data;
• and
• an additional memory associated with the next lower level cache memory and including a plurality of memory lines, each memory line of the additional memory including respective L-flags for multiple cache lines of each way set of the next lower level cache memory, and all L-flags associated with a given one of the indices plus any index offset from the first level cache memory are contained in a single memory line of the additional memory;
• wherein the next lower level cache memory does not include an L-flag contained within each cache line thereof;
• wherein each L-flag indicates whether any of the cache lines of the first level cache memory contains a copy of the data stored in a given cache line of the next lower level cache memory and respective L-flags are set to indicate whether or not corresponding cache lines of the first level cache memory have been refilled with data stored in the cache lines of the next lower level cache memory;
• and
• wherein data overwriting into the given cache line is prohibited when the L-flag of the given cache line indicates that a corresponding one the of the cache lines of the first level cache memory contains a copy of the data stored in the given cache line of the next lower level cache memory.

A method, comprising:

• controlling a first level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the first level cache memory being operable to store an address tag and data, and each cache line having an index associated therewith;
• controlling a next lower level cache memory including a plurality of way sets and a plurality of cache lines associated therewith, each cache line of the next lower level cache memory being operable to store an address tag, status flags, and data;
• controlling an additional memory associated with the next lower level cache memory and including a plurality of memory lines, each memory line of the additional memory including respective L-flags for multiple cache lines of each way set of the next lower level cache memory, and all L-flags associated with a given one of the indices plus any index offset from the first level cache memory are contained in a single memory line of the additional memory;
• and
• setting the respective L-flags of the additional memory to indicate whether or not corresponding cache lines of the first level cache memory have been refilled with data stored in the cache lines of the next lower level cache memory;
• wherein the next lower level cache memory does not include an L-flag contained within each cache line thereof;
• wherein each L-flag indicates whether any of the cache lines of the first level cache memory contains a copy of the data stored in a given cache line of the next lower level cache memory;
• and
• wherein data overwriting into the given cache line is prohibited when the L-flag of the given cache line indicates that a corresponding one the of the cache lines of the first level cache memory contains a copy of the data stored in the given cache line of the next lower level cache memory.