Method of uniforming physical random number and physical number generation device

A physical random number generation device comprising a physical random number generator, the physical random number generator comprising:

• a serial physical random number generator for generating a serial random number in accordance with a reference clock signal;
• a serial/parallel converter for converting the serial random number to a parallel random number;
• a plurality of registers capable of storing the parallel random number;
• and
• a control circuit for (i) sequentially storing the parallel random number in the plurality of registers each time the parallel random number is generated by the serial/parallel converter, (ii) reading and outputting the parallel random number from the plurality of registers in accordance with a read clock signal, and (iii) successively updating contents of the plurality of registers by shifting the stored parallel random number from a register of the plurality of registers to another register of the plurality of registers, the other register being a register for which the reading of the parallel random number has completed.

A physical random number generator comprising:

• two integration circuits, each integration circuit for integrating a clock signal through a resistor and a capacitor to output a respective integral waveform;
• two noise sources;
• two amplifiers, each amplifier for amplifying a noise from a respective noise source of the two noise sources, to output a respective noise signal;
• two mixers, each mixer for mixing a respective integral waveform and a respective noise signal;
• two edge detection circuits, each edge detection circuit for detecting a first edge of jitter generated based on an output waveform of a respective mixer of the two mixers;
• a flip-flop for outputting “0” or “1” based on a phase differences between respective output signals output from the two edge detection circuits;
• a phase adjuster for adjusting a phase of an input signal input into each integration circuit, the phase adjuster including a delay, a first selector and an up/down counter;
• and
• a feedback circuit for feeding back the output of the flip-flop to the phase adjuster so that the “0” or the “1” output from the flip-flop converges to 50%;
• wherein a second selector and a third selector are provided at a former stage of each integration circuit, respectively, and
• wherein the physical random number generator includes a polarity switching circuit for switching a polarity of an input to the first selector, the second selector and the third selector by a most significant bit of the up/down counter.

A physical random number generator comprising:

• one integration circuit for integrating a clock signal through a resistor and a capacitor to output an integral waveform;
• two noise sources;
• two amplifiers, each amplifier for amplifying a noise from a respective noise source of the two noise sources, to output a respective noise signal;
• two mixers, each mixer for mixing the integral waveform and a respective noise signal;
• two edge detection circuits, each edge detection circuit for detecting a first edge of jitter generated based on an output waveform of a respective mixer of the two mixers;
• and
• a flip-flop for outputting “0” or “1” based on a phase differences between respective output signals output from the two edge detection circuits;
• wherein a variable delay, including a delay and a selector, for adjusting a phase of an input signal input into the flip-flop is provided at a former or latter stage of each edge detection circuit, and
• wherein the physical random number generator includes a feedback circuit for feeding back the output of the flip-flop to the variable delay so that the “0” or the “1” output from the flip-flop converges to 50%.

A physical random number generator comprising:

• two integration circuits, each integration circuit for integrating a clock signal using a constant current circuit and a capacitor to output a respective integral waveform;
• two noise sources;
• two amplifiers, each amplifier for amplifying a noise from a respective noise source of the two noise sources, to output a respective noise signal;
• two mixers, each mixer for mixing a respective integral waveform and a respective noise signal;
• two edge detection circuits each edge detection circuit for detecting a first edge of jitter generated based on an output waveform of a respective mixer of the two mixers;
• a flip-flop for outputting “0” or “1” based on a phase difference between respective output signals output from the two edge detection circuits;
• a phase adjuster for adjusting a phase of an input signal input into each integration circuit, the phase adjuster including a delay, a first selector and an up/down counter;
• and
• a feedback circuit for feeding back the output of the flip-flop to the phase adjuster so that the “0” or the “1” output from the flip-flop converges to 50%;
• wherein a second selector and a third selector are provided at a former stage of each integration circuit, respectively, and
• wherein the physical random number generator includes a polarity switching circuit for switching a polarity of an input to the first selector, the second selector and the third selector by a most significant bit of the up/down counter.

A physical random number generator comprising:

• one integration circuit for integrating a clock signal using a constant current circuit and a capacitor to output an integral waveform;
• two noise sources;
• two amplifiers each amplifier for amplifying a noise from a respective noise source of the two noise sources, to output a respective noise signal;
• two mixers, each mixer for mixing the integral waveform and a respective noise signal;
• two edge detection circuits, each edge detection circuit for detecting a first edge of jitter generated based on an output waveform of a respective mixer of the two mixers;
• and
• a flip-flop for outputting “0” or “1” based on a phase difference between respective output signals output from the two edge detection circuits;
• wherein a variable delay, including a delay and a selector, for adjusting a phase of an input signal input into the flip-flop is provided at a former or latter stage of each edge detection circuit, and
• wherein the physical random number generator includes a feedback circuit for feeding back the output of the flip-flop to the variable delay so that the “0” or the “1” output from the flip-flop converges to 50%.